Initial commit.
This commit is contained in:
SiFive
28
src/main/scala/unleashed/u500vc707devkit/Configs.scala
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28
src/main/scala/unleashed/u500vc707devkit/Configs.scala
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// See LICENSE for license details.
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package sifive.freedom.unleashed.u500vc707devkit
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import config._
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import coreplex.{WithL1DCacheWays, WithSmallCores, WithoutFPU, BootROMFile}
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import rocketchip.{BaseConfig,WithRTCPeriod,WithJtagDTM}
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// Don't use directly. Requires additional bootfile configuration
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class DefaultFreedomUConfig extends Config(
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new WithJtagDTM ++ new BaseConfig
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)
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class WithBootROMFile(bootROMFile: String) extends Config(
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(pname, site, here) => pname match {
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case BootROMFile => bootROMFile
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case _ => throw new CDEMatchError
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}
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)
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//----------------------------------------------------------------------------------
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// Freedom U500 VC707 Dev Kit
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class U500VC707DevKitConfig extends Config(
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new WithBootROMFile("./bootrom/u500vc707devkit.img") ++
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new WithRTCPeriod(62) ++ //Default value of 100 generates 1 Mhz clock @ 100Mhz, then corrected in sbi_entry.c
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//Value 62 generates ~ 1Mhz clock @ 62.5Mhz
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new WithoutFPU ++
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new DefaultFreedomUConfig)
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299
src/main/scala/unleashed/u500vc707devkit/Top.scala
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299
src/main/scala/unleashed/u500vc707devkit/Top.scala
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// See LICENSE for license details.
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package sifive.freedom.unleashed.u500vc707devkit
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import Chisel._
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import config._
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import util._
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import junctions._
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import diplomacy._
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import uncore.tilelink._
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import uncore.devices._
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import uncore.util._
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import uncore.converters._
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import rocket._
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import coreplex._
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import rocketchip._
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import sifive.blocks.devices.xilinxvc707mig._
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import sifive.blocks.devices.xilinxvc707pciex1._
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import sifive.blocks.devices.gpio.{GPIOConfig, PeripheryGPIO, PeripheryGPIOBundle, PeripheryGPIOModule}
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import sifive.blocks.devices.spi.{SPIConfig, PeripherySPI, PeripherySPIBundle, PeripherySPIModule}
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import sifive.blocks.devices.uart._
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import sifive.blocks.util.ResetCatchAndSync
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trait PeripheryConfigs {
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val uartConfigs = List(UARTConfig(address = BigInt(0x54000000L)))
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val spiConfigs = List(SPIConfig(rAddress = BigInt(0x54001000L)))
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val gpioConfig = GPIOConfig(address = BigInt(0x54002000L), width = 4)
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}
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class U500VC707DevKitSystem(implicit p: Parameters) extends BaseTop
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with PeripheryConfigs
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with PeripheryBootROM
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with PeripheryDebug
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with PeripheryCounter
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with PeripheryUART
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with PeripherySPI
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with PeripheryGPIO
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with PeripheryXilinxVC707MIG
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with PeripheryXilinxVC707PCIeX1
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with HardwiredResetVector
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with RocketPlexMaster {
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override lazy val module = new U500VC707DevKitSystemModule(this, () => new U500VC707DevKitSystemBundle(this))
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// scalastyle:off method.length
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ConfigStringOutput.contents = Some {
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"""platform {
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| vendor ucb;
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| arch spike;
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|};
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|plic {
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| interface "plic";
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| ndevs 9;
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| priority { mem { 0x0c000000 0x0c00ffff; }; };
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| pending { mem { 0x0c001000 0x0c00107f; }; };
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| 0 {
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| 0 {
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| m {
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| ie { mem { 0x0c002000 0x0c00207f; }; };
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| ctl { mem { 0x0c200000 0x0c200007; }; };
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| };
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| s {
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| ie { mem { 0x0c002080 0x0c0020ff; }; };
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| ctl { mem { 0x0c201000 0x0c201007; }; };
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| };
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| };
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| };
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|};
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|pcie {
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| interface "xilinx-pcie-rv";
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| bus {
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| mem { 0x60000000 0x7fffffff; } { 0x200000000 0x3ffffffff; };
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| bus { 1 63; };
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| };
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| bridge {
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| mem { 0x50000000 0x53ffffff; };
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| bus 0;
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| irq 6;
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| };
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|};
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|leds {
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| interface "gpio";
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| ngpio 4;
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| mem { 0x54002000 0x54002003; };
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|};
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|rtc {
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| addr 0x200bff8;
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|};
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|ram {
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| 0 {
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| addr 0x80000000;
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| size 0x10000000;
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| };
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|};
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|uart {
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| addr 0x54000000;
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|};
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|core {
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| 0 {
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| 0 {
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| isa rv64ima;
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| timecmp 0x02004000;
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| ipi 0x02000000;
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| };
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| };
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|};
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|\u0000""".stripMargin
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}
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// scalastyle:on method.length
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}
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class U500VC707DevKitSystemBundle[+L <: U500VC707DevKitSystem](_outer: L) extends BaseTopBundle(_outer)
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with PeripheryConfigs
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with PeripheryBootROMBundle
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with PeripheryDebugBundle
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with PeripheryCounterBundle
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with PeripheryUARTBundle
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with PeripherySPIBundle
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with PeripheryGPIOBundle
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with PeripheryXilinxVC707MIGBundle
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with PeripheryXilinxVC707PCIeX1Bundle
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with HardwiredResetVectorBundle
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with RocketPlexMasterBundle
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class U500VC707DevKitSystemModule[+L <: U500VC707DevKitSystem, +B <: U500VC707DevKitSystemBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
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with PeripheryConfigs
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with PeripheryBootROMModule
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with PeripheryDebugModule
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with PeripheryCounterModule
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with PeripheryUARTModule
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with PeripherySPIModule
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with PeripheryGPIOModule
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with PeripheryXilinxVC707MIGModule
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with PeripheryXilinxVC707PCIeX1Module
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with HardwiredResetVectorModule
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with RocketPlexMasterModule
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/////
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class ResetDone extends Module {
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//unused - in future io.resetdone can set rocketchip STOP_COND/PRINTF_COND
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val io = new Bundle{
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val reset = Bool(INPUT)
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val resetdone = Bool(OUTPUT)
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}
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val resetdonereg = Reg(init = Bool(false))
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val resetff = Reg(init = Bool(false))
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resetff := io.reset;
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resetdonereg := Mux( ((!io.reset)&&resetff), UInt("b1"), resetdonereg)
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io.resetdone := resetdonereg
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}
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/////
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class U500VC707DevKitIO(implicit val p: Parameters) extends Bundle
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with PeripheryConfigs
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with PeripheryUARTBundle
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with PeripherySPIBundle
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with PeripheryGPIOBundle
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{
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val debug = (!p(IncludeJtagDTM)).option(new DebugBusIO()(p).flip)
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val jtag = p(IncludeJtagDTM).option(new JTAGIO(true).flip)
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//MIG
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val xilinxvc707mig = new XilinxVC707MIGPads
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//PCIe
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val xilinxvc707pcie = new XilinxVC707PCIeX1Pads
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//Clocks
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val sys_clk_n = Bool(INPUT)
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val sys_clk_p = Bool(INPUT)
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val pcie_refclk_p = Bool(INPUT)
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val pcie_refclk_n = Bool(INPUT)
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//Reset
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val sys_reset = Bool(INPUT)
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//Misc outputs used in system.v
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val core_reset = Bool(OUTPUT)
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val core_clock = Clock(OUTPUT)
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}
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/////
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class U500VC707DevKitTop(implicit val p: Parameters) extends Module {
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// ------------------------------------------------------------
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// Instantiate U500 VC707 Dev Kit system (sys)
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// ------------------------------------------------------------
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val sys = Module(LazyModule(new U500VC707DevKitSystem).module)
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val io = new U500VC707DevKitIO
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// ------------------------------------------------------------
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// Clock and Reset
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// ------------------------------------------------------------
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val mig_mmcm_locked = Wire(Bool())
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val mig_sys_reset = Wire(Bool())
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val init_calib_complete = Wire(Bool())
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val mmcm_lock_pcie = Wire(Bool())
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val do_reset = Wire(Bool())
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val mig_clock = Wire(Clock())
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val mig_resetn = Wire(Bool())
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val top_resetn = Wire(Bool())
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val pcie_dat_reset = Wire(Bool())
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val pcie_dat_resetn = Wire(Bool())
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val pcie_cfg_reset = Wire(Bool())
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val pcie_cfg_resetn = Wire(Bool())
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val pcie_dat_clock = Wire(Clock())
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val pcie_cfg_clock = Wire(Clock())
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val top_clock = Wire(Clock())
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val top_reset = Wire(Bool())
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val mig_reset = Wire(Bool())
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do_reset := !mig_mmcm_locked || !mmcm_lock_pcie || mig_sys_reset
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mig_resetn := !mig_reset
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top_resetn := !top_reset
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pcie_dat_resetn := !pcie_dat_reset
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pcie_cfg_resetn := !pcie_cfg_reset
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// For now, run the CPU synchronous to the PCIe data bus
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top_clock := pcie_dat_clock
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val safe_reset = Module(new vc707reset)
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safe_reset.io.areset := do_reset
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safe_reset.io.clock1 := mig_clock
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mig_reset := safe_reset.io.reset1
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safe_reset.io.clock2 := pcie_dat_clock
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pcie_dat_reset := safe_reset.io.reset2
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safe_reset.io.clock3 := pcie_cfg_clock
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pcie_cfg_reset := safe_reset.io.reset3
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safe_reset.io.clock4 := top_clock
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top_reset := safe_reset.io.reset4
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sys.clock := top_clock
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sys.reset := top_reset
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// ------------------------------------------------------------
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// UART
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// ------------------------------------------------------------
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io.uarts <> sys.io.uarts
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// ------------------------------------------------------------
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// SPI
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// ------------------------------------------------------------
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io.spis <> sys.io.spis
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// ------------------------------------------------------------
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// GPIO
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// ------------------------------------------------------------
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io.gpio <> sys.io.gpio
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// ------------------------------------------------------------
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// MIG
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// ------------------------------------------------------------
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sys.io.xilinxvc707mig.sys_clk_p := io.sys_clk_p
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sys.io.xilinxvc707mig.sys_clk_n := io.sys_clk_n
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mig_clock := sys.io.xilinxvc707mig.ui_clk
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mig_sys_reset := sys.io.xilinxvc707mig.ui_clk_sync_rst
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mig_mmcm_locked := sys.io.xilinxvc707mig.mmcm_locked
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sys.io.xilinxvc707mig.aresetn := mig_resetn
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init_calib_complete := sys.io.xilinxvc707mig.init_calib_complete
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sys.io.xilinxvc707mig.sys_rst := io.sys_reset
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//the below bundle assignment is dangerous and relies on matching signal names
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// io.xilinxvc707 is of type XilinxVC707MIGPads
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// sys.io.xilinxvc707mig is of type XilinxVC707MIGIO
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io.xilinxvc707mig <> sys.io.xilinxvc707mig
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// ------------------------------------------------------------
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// PCIe
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// ------------------------------------------------------------
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sys.io.xilinxvc707pcie.axi_aresetn := pcie_dat_resetn
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pcie_dat_clock := sys.io.xilinxvc707pcie.axi_aclk_out
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pcie_cfg_clock := sys.io.xilinxvc707pcie.axi_ctl_aclk_out
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mmcm_lock_pcie := sys.io.xilinxvc707pcie.mmcm_lock
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sys.io.xilinxvc707pcie.axi_ctl_aresetn := pcie_dat_resetn
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sys.io.xilinxvc707pcie.REFCLK_rxp := io.pcie_refclk_p
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sys.io.xilinxvc707pcie.REFCLK_rxn := io.pcie_refclk_n
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//another dangerous bundle assignment which relies on matching signal names
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// io.xilinxvc707pcie is of type XilinxVC707PCIeX1Pads
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// sys.io.xilinxvc707pcie is of type XilinxVC707PCIeX1IO
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io.xilinxvc707pcie <> sys.io.xilinxvc707pcie
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// ------------------------------------------------------------
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// Debug
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// ------------------------------------------------------------
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if (p(IncludeJtagDTM)) {
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sys.io.jtag.get <> io.jtag.get
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//Override TRST to reset this logic IFF the core is in reset.
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// This will require 3 ticks of TCK before the debug logic
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// comes out of reset, but JTAG needs 5 ticks anyway.
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// This means that the "real" TRST is never actually used.
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sys.io.jtag.get.TRST := ResetCatchAndSync(sys.io.jtag.get.TCK, top_reset)
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}else{
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// SimDTM; only for simulation use
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sys.io.debug.get := io.debug.get
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// test_mode_clk shouldn't be used for simulation
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//sys.io.test_mode_clk := Bool(false).asClock
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}
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// ------------------------------------------------------------
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// Misc outputs used in system.v
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// ------------------------------------------------------------
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io.core_clock := top_clock
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io.core_reset := top_reset
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}
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22
src/main/scala/unleashed/u500vc707devkit/vc707reset.scala
Normal file
22
src/main/scala/unleashed/u500vc707devkit/vc707reset.scala
Normal file
@@ -0,0 +1,22 @@
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// See LICENSE for license details.
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package sifive.freedom.unleashed.u500vc707devkit
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import Chisel._
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//scalastyle:off
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//turn off linter: blackbox name must match verilog module
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class vc707reset() extends BlackBox
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{
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val io = new Bundle{
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val areset = Bool(INPUT)
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val clock1 = Clock(INPUT)
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val reset1 = Bool(OUTPUT)
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val clock2 = Clock(INPUT)
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val reset2 = Bool(OUTPUT)
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val clock3 = Clock(INPUT)
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val reset3 = Bool(OUTPUT)
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val clock4 = Clock(INPUT)
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val reset4 = Bool(OUTPUT)
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}
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}
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//scalastyle:on
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