Initial commit.
This commit is contained in:
SiFive
37
src/main/scala/everywhere/e300artydevkit/Configs.scala
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37
src/main/scala/everywhere/e300artydevkit/Configs.scala
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// See LICENSE for license details.
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package sifive.freedom.everywhere.e300artydevkit
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import config._
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import coreplex._
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import rocketchip._
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class DefaultFreedomEConfig extends Config(
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new WithStatelessBridge ++
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new WithNBreakpoints(2) ++
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new WithRV32 ++
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new DefaultSmallConfig
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)
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class WithBootROMFile(bootROMFile: String) extends Config(
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(pname, site, here) => pname match {
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case BootROMFile => bootROMFile
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case _ => throw new CDEMatchError
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}
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)
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class E300ArtyDevKitConfig extends Config(
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new WithBootROMFile("./bootrom/e300artydevkit.img") ++
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new WithNExtTopInterrupts(0) ++
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new WithJtagDTM ++
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new WithL1ICacheSets(8192/32) ++ // 8 KiB **per set**
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new WithCacheBlockBytes(32) ++
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new WithL1ICacheWays(2) ++
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new WithDefaultBtb ++
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new WithFastMulDiv ++
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new WithDataScratchpad(16384) ++
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new WithNMemoryChannels(0) ++
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new WithoutFPU ++
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new WithTLMonitors ++
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new DefaultFreedomEConfig
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)
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230
src/main/scala/everywhere/e300artydevkit/Top.scala
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230
src/main/scala/everywhere/e300artydevkit/Top.scala
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// See LICENSE for license details.
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package sifive.freedom.everywhere.e300artydevkit
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import Chisel._
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import config._
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import diplomacy._
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import coreplex._
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import rocketchip._
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import uncore.devices.DebugBusIO
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import sifive.blocks.devices.gpio.{GPIOConfig, PeripheryGPIO, PeripheryGPIOBundle, PeripheryGPIOModule, GPIOPin, GPIOPinToIOF, GPIOPinIOFCtrl, GPIOInputPinCtrl, JTAGPinsIO, JTAGGPIOPort}
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import sifive.blocks.devices.mockaon.{MockAONConfig, PeripheryMockAON, PeripheryMockAONBundle, PeripheryMockAONModule, MockAONWrapperPadsIO}
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import sifive.blocks.devices.pwm.{PWMConfig, PeripheryPWM, PeripheryPWMBundle, PeripheryPWMModule, PWMGPIOPort}
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import sifive.blocks.devices.spi.{SPIConfig, PeripherySPI, PeripherySPIBundle, PeripherySPIModule, SPIFlashConfig, PeripherySPIFlash, PeripherySPIFlashBundle, PeripherySPIFlashModule, SPIPinsIO, SPIGPIOPort}
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import sifive.blocks.devices.uart.{UARTConfig, PeripheryUART, PeripheryUARTBundle, PeripheryUARTModule, UARTGPIOPort}
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import sifive.blocks.util.ResetCatchAndSync
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import util._
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// Coreplex and Periphery
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trait E300ArtyDevKitPeripheryConfigs {
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val mockAONConfig = MockAONConfig(address = 0x10000000)
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val gpioConfig = GPIOConfig(address = 0x10012000, width = 32)
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val pwmConfigs = List(
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PWMConfig(address = 0x10015000, cmpWidth = 8),
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PWMConfig(address = 0x10025000, cmpWidth = 16),
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PWMConfig(address = 0x10035000, cmpWidth = 16))
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val spiConfigs = List(
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SPIConfig(csWidth = 4, rAddress = 0x10024000, sampleDelay = 3),
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SPIConfig(csWidth = 1, rAddress = 0x10034000, sampleDelay = 3))
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val spiFlashConfig = SPIFlashConfig(
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fAddress = 0x20000000, rAddress = 0x10014000, sampleDelay = 3)
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val uartConfigs = List(
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UARTConfig(address = 0x10013000),
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UARTConfig(address = 0x10023000))
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}
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// This custom E300ArtyDevKit coreplex has no port into the L2 and no memory subsystem
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class E300ArtyDevKitCoreplex(implicit p: Parameters) extends BareCoreplex
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with CoreplexNetwork
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with CoreplexRISCVPlatform
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with RocketTiles {
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override lazy val module = new E300ArtyDevKitCoreplexModule(this, () => new E300ArtyDevKitCoreplexBundle(this))
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}
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class E300ArtyDevKitCoreplexBundle[+L <: E300ArtyDevKitCoreplex](_outer: L) extends BareCoreplexBundle(_outer)
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with CoreplexNetworkBundle
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with CoreplexRISCVPlatformBundle
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with RocketTilesBundle
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class E300ArtyDevKitCoreplexModule[+L <: E300ArtyDevKitCoreplex, +B <: E300ArtyDevKitCoreplexBundle[L]](_outer: L, _io: () => B)
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extends BareCoreplexModule(_outer, _io)
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with CoreplexNetworkModule
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with CoreplexRISCVPlatformModule
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with RocketTilesModule
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class E300ArtyDevKitSystem(implicit p: Parameters) extends BaseTop
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with E300ArtyDevKitPeripheryConfigs
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with PeripheryBootROM
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with PeripheryDebug
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with PeripheryMockAON
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with PeripheryUART
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with PeripherySPIFlash
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with PeripherySPI
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with PeripheryGPIO
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with PeripheryPWM
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with HardwiredResetVector {
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override lazy val module = new E300ArtyDevKitSystemModule(this, () => new E300ArtyDevKitSystemBundle(this))
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val coreplex = LazyModule(new E300ArtyDevKitCoreplex)
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socBus.node := coreplex.mmio
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coreplex.mmioInt := intBus.intnode
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}
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class E300ArtyDevKitSystemBundle[+L <: E300ArtyDevKitSystem](_outer: L) extends BaseTopBundle(_outer)
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with E300ArtyDevKitPeripheryConfigs
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with PeripheryBootROMBundle
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with PeripheryDebugBundle
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with PeripheryUARTBundle
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with PeripherySPIBundle
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with PeripheryGPIOBundle
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with PeripherySPIFlashBundle
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with PeripheryMockAONBundle
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with PeripheryPWMBundle
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with HardwiredResetVectorBundle
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class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem, +B <: E300ArtyDevKitSystemBundle[L]](_outer: L, _io: () => B)
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extends BaseTopModule(_outer, _io)
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with E300ArtyDevKitPeripheryConfigs
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with PeripheryBootROMModule
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with PeripheryDebugModule
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with PeripheryUARTModule
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with PeripherySPIModule
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with PeripheryGPIOModule
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with PeripherySPIFlashModule
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with PeripheryMockAONModule
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with PeripheryPWMModule
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with HardwiredResetVectorModule
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// Top
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class E300ArtyDevKitTopIO(implicit val p: Parameters) extends Bundle with E300ArtyDevKitPeripheryConfigs {
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val pads = new Bundle {
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val jtag = new JTAGPinsIO
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val gpio = Vec(gpioConfig.width, new GPIOPin)
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val qspi = new SPIPinsIO(spiFlashConfig)
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val aon = new MockAONWrapperPadsIO()
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}
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}
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class E300ArtyDevKitTop(implicit val p: Parameters) extends Module with E300ArtyDevKitPeripheryConfigs {
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val sys = Module(LazyModule(new E300ArtyDevKitSystem).module)
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val io = new E300ArtyDevKitTopIO
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// This needs to be de-asserted synchronously to the coreClk.
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val async_corerst = sys.io.aon.rsts.corerst
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sys.reset := ResetCatchAndSync(clock, async_corerst, 20)
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// ------------------------------------------------------------
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// Check for unsupported RCT Connections
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// ------------------------------------------------------------
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require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported");
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// ------------------------------------------------------------
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// Build GPIO Pin Mux
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// ------------------------------------------------------------
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// Pin Mux for UART, SPI, PWM
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// First convert the System outputs into "IOF" using the respective *GPIOPort
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// converters.
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val sys_uarts = sys.io.uarts
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val sys_pwms = sys.io.pwms
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val sys_spis = sys.io.spis
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val uart_pins = uartConfigs.map { c => Module (new UARTGPIOPort) }
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val pwm_pins = pwmConfigs.map { c => Module (new PWMGPIOPort(c.bc)) }
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val spi_pins = spiConfigs.map { c => Module (new SPIGPIOPort(c)) }
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(uart_pins zip sys_uarts) map {case (p, r) => p.io.uart <> r}
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(pwm_pins zip sys_pwms) map {case (p, r) => p.io.pwm <> r}
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(spi_pins zip sys_spis) map {case (p, r) => p.io.spi <> r}
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// ------------------------------------------------------------
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// Default Pin connections before attaching pinmux
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for (iof_0 <- sys.io.gpio.iof_0) {
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iof_0.o := GPIOPinIOFCtrl()
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}
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for (iof_1 <- sys.io.gpio.iof_1) {
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iof_1.o := GPIOPinIOFCtrl()
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}
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// ------------------------------------------------------------
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// TODO: Make this mapping more programmatic.
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val iof_0 = sys.io.gpio.iof_0
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val iof_1 = sys.io.gpio.iof_1
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// SPI1 (0 is the dedicated)
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GPIOPinToIOF(spi_pins(0).io.pins.cs(0), iof_0(2))
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GPIOPinToIOF(spi_pins(0).io.pins.dq(0), iof_0(3))
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GPIOPinToIOF(spi_pins(0).io.pins.dq(1), iof_0(4))
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GPIOPinToIOF(spi_pins(0).io.pins.sck, iof_0(5))
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GPIOPinToIOF(spi_pins(0).io.pins.dq(2), iof_0(6))
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GPIOPinToIOF(spi_pins(0).io.pins.dq(3), iof_0(7))
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GPIOPinToIOF(spi_pins(0).io.pins.cs(1), iof_0(8))
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GPIOPinToIOF(spi_pins(0).io.pins.cs(2), iof_0(9))
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GPIOPinToIOF(spi_pins(0).io.pins.cs(3), iof_0(10))
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// SPI2
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GPIOPinToIOF(spi_pins(1).io.pins.cs(0), iof_0(26))
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GPIOPinToIOF(spi_pins(1).io.pins.dq(0), iof_0(27))
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GPIOPinToIOF(spi_pins(1).io.pins.dq(1), iof_0(28))
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GPIOPinToIOF(spi_pins(1).io.pins.sck, iof_0(29))
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GPIOPinToIOF(spi_pins(1).io.pins.dq(2), iof_0(30))
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GPIOPinToIOF(spi_pins(1).io.pins.dq(3), iof_0(31))
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// UART0
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GPIOPinToIOF(uart_pins(0).io.pins.rxd, iof_0(16))
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GPIOPinToIOF(uart_pins(0).io.pins.txd, iof_0(17))
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// UART1
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GPIOPinToIOF(uart_pins(1).io.pins.rxd, iof_0(24))
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GPIOPinToIOF(uart_pins(1).io.pins.txd, iof_0(25))
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//PWM
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GPIOPinToIOF(pwm_pins(0).io.pins.pwm(0), iof_1(0) )
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GPIOPinToIOF(pwm_pins(0).io.pins.pwm(1), iof_1(1) )
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GPIOPinToIOF(pwm_pins(0).io.pins.pwm(2), iof_1(2) )
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GPIOPinToIOF(pwm_pins(0).io.pins.pwm(3), iof_1(3) )
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GPIOPinToIOF(pwm_pins(1).io.pins.pwm(1), iof_1(19))
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GPIOPinToIOF(pwm_pins(1).io.pins.pwm(0), iof_1(20))
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GPIOPinToIOF(pwm_pins(1).io.pins.pwm(2), iof_1(21))
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GPIOPinToIOF(pwm_pins(1).io.pins.pwm(3), iof_1(22))
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GPIOPinToIOF(pwm_pins(2).io.pins.pwm(0), iof_1(10))
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GPIOPinToIOF(pwm_pins(2).io.pins.pwm(1), iof_1(11))
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GPIOPinToIOF(pwm_pins(2).io.pins.pwm(2), iof_1(12))
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GPIOPinToIOF(pwm_pins(2).io.pins.pwm(3), iof_1(13))
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// ------------------------------------------------------------
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// Drive actual Pads
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// ------------------------------------------------------------
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// Result of Pin Mux
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io.pads.gpio <> sys.io.gpio.pins
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val dedicated_spi_pins = Module (new SPIGPIOPort(spiFlashConfig, syncStages=3, driveStrength=Bool(true)))
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dedicated_spi_pins.clock := sys.clock
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dedicated_spi_pins.reset := sys.reset
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io.pads.qspi <> dedicated_spi_pins.io.pins
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dedicated_spi_pins.io.spi <> sys.io.qspi
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// JTAG Debug Interface
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val jtag_pins = Module (new JTAGGPIOPort(true))
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io.pads.jtag <> jtag_pins.io.pins
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sys.io.jtag.get <> jtag_pins.io.jtag
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// Override TRST to reset this logic IFF the core is in reset.
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// This will require 3 ticks of TCK before the debug logic
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// comes out of reset, but JTAG needs 5 ticks anyway.
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// This means that the "real" TRST is never actually used in this design.
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sys.io.jtag.get.TRST := ResetCatchAndSync(sys.io.jtag.get.TCK, async_corerst)
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// AON Pads
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io.pads.aon <> sys.io.aon.pads
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}
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