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SiFive
2016-11-29 05:23:11 -08:00
commit 3cf8128a30
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37
src/main/scala/everywhere/e300artydevkit/Configs.scala Normal file
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// See LICENSE for license details.
package sifive.freedom.everywhere.e300artydevkit
import config._
import coreplex._
import rocketchip._
class DefaultFreedomEConfig extends Config(
new WithStatelessBridge ++
new WithNBreakpoints(2) ++
new WithRV32 ++
new DefaultSmallConfig
)
class WithBootROMFile(bootROMFile: String) extends Config(
(pname, site, here) => pname match {
case BootROMFile => bootROMFile
case _ => throw new CDEMatchError
}
)
class E300ArtyDevKitConfig extends Config(
new WithBootROMFile("./bootrom/e300artydevkit.img") ++
new WithNExtTopInterrupts(0) ++
new WithJtagDTM ++
new WithL1ICacheSets(8192/32) ++ // 8 KiB **per set**
new WithCacheBlockBytes(32) ++
new WithL1ICacheWays(2) ++
new WithDefaultBtb ++
new WithFastMulDiv ++
new WithDataScratchpad(16384) ++
new WithNMemoryChannels(0) ++
new WithoutFPU ++
new WithTLMonitors ++
new DefaultFreedomEConfig
)

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src/main/scala/everywhere/e300artydevkit/Top.scala Normal file
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// See LICENSE for license details.
package sifive.freedom.everywhere.e300artydevkit
import Chisel._
import config._
import diplomacy._
import coreplex._
import rocketchip._
import uncore.devices.DebugBusIO
import sifive.blocks.devices.gpio.{GPIOConfig, PeripheryGPIO, PeripheryGPIOBundle, PeripheryGPIOModule, GPIOPin, GPIOPinToIOF, GPIOPinIOFCtrl, GPIOInputPinCtrl, JTAGPinsIO, JTAGGPIOPort}
import sifive.blocks.devices.mockaon.{MockAONConfig, PeripheryMockAON, PeripheryMockAONBundle, PeripheryMockAONModule, MockAONWrapperPadsIO}
import sifive.blocks.devices.pwm.{PWMConfig, PeripheryPWM, PeripheryPWMBundle, PeripheryPWMModule, PWMGPIOPort}
import sifive.blocks.devices.spi.{SPIConfig, PeripherySPI, PeripherySPIBundle, PeripherySPIModule, SPIFlashConfig, PeripherySPIFlash, PeripherySPIFlashBundle, PeripherySPIFlashModule, SPIPinsIO, SPIGPIOPort}
import sifive.blocks.devices.uart.{UARTConfig, PeripheryUART, PeripheryUARTBundle, PeripheryUARTModule, UARTGPIOPort}
import sifive.blocks.util.ResetCatchAndSync
import util._
// Coreplex and Periphery
trait E300ArtyDevKitPeripheryConfigs {
val mockAONConfig = MockAONConfig(address = 0x10000000)
val gpioConfig = GPIOConfig(address = 0x10012000, width = 32)
val pwmConfigs = List(
PWMConfig(address = 0x10015000, cmpWidth = 8),
PWMConfig(address = 0x10025000, cmpWidth = 16),
PWMConfig(address = 0x10035000, cmpWidth = 16))
val spiConfigs = List(
SPIConfig(csWidth = 4, rAddress = 0x10024000, sampleDelay = 3),
SPIConfig(csWidth = 1, rAddress = 0x10034000, sampleDelay = 3))
val spiFlashConfig = SPIFlashConfig(
fAddress = 0x20000000, rAddress = 0x10014000, sampleDelay = 3)
val uartConfigs = List(
UARTConfig(address = 0x10013000),
UARTConfig(address = 0x10023000))
}
// This custom E300ArtyDevKit coreplex has no port into the L2 and no memory subsystem
class E300ArtyDevKitCoreplex(implicit p: Parameters) extends BareCoreplex
with CoreplexNetwork
with CoreplexRISCVPlatform
with RocketTiles {
override lazy val module = new E300ArtyDevKitCoreplexModule(this, () => new E300ArtyDevKitCoreplexBundle(this))
}
class E300ArtyDevKitCoreplexBundle[+L <: E300ArtyDevKitCoreplex](_outer: L) extends BareCoreplexBundle(_outer)
with CoreplexNetworkBundle
with CoreplexRISCVPlatformBundle
with RocketTilesBundle
class E300ArtyDevKitCoreplexModule[+L <: E300ArtyDevKitCoreplex, +B <: E300ArtyDevKitCoreplexBundle[L]](_outer: L, _io: () => B)
extends BareCoreplexModule(_outer, _io)
with CoreplexNetworkModule
with CoreplexRISCVPlatformModule
with RocketTilesModule
class E300ArtyDevKitSystem(implicit p: Parameters) extends BaseTop
with E300ArtyDevKitPeripheryConfigs
with PeripheryBootROM
with PeripheryDebug
with PeripheryMockAON
with PeripheryUART
with PeripherySPIFlash
with PeripherySPI
with PeripheryGPIO
with PeripheryPWM
with HardwiredResetVector {
override lazy val module = new E300ArtyDevKitSystemModule(this, () => new E300ArtyDevKitSystemBundle(this))
val coreplex = LazyModule(new E300ArtyDevKitCoreplex)
socBus.node := coreplex.mmio
coreplex.mmioInt := intBus.intnode
}
class E300ArtyDevKitSystemBundle[+L <: E300ArtyDevKitSystem](_outer: L) extends BaseTopBundle(_outer)
with E300ArtyDevKitPeripheryConfigs
with PeripheryBootROMBundle
with PeripheryDebugBundle
with PeripheryUARTBundle
with PeripherySPIBundle
with PeripheryGPIOBundle
with PeripherySPIFlashBundle
with PeripheryMockAONBundle
with PeripheryPWMBundle
with HardwiredResetVectorBundle
class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem, +B <: E300ArtyDevKitSystemBundle[L]](_outer: L, _io: () => B)
extends BaseTopModule(_outer, _io)
with E300ArtyDevKitPeripheryConfigs
with PeripheryBootROMModule
with PeripheryDebugModule
with PeripheryUARTModule
with PeripherySPIModule
with PeripheryGPIOModule
with PeripherySPIFlashModule
with PeripheryMockAONModule
with PeripheryPWMModule
with HardwiredResetVectorModule
// Top
class E300ArtyDevKitTopIO(implicit val p: Parameters) extends Bundle with E300ArtyDevKitPeripheryConfigs {
val pads = new Bundle {
val jtag = new JTAGPinsIO
val gpio = Vec(gpioConfig.width, new GPIOPin)
val qspi = new SPIPinsIO(spiFlashConfig)
val aon = new MockAONWrapperPadsIO()
}
}
class E300ArtyDevKitTop(implicit val p: Parameters) extends Module with E300ArtyDevKitPeripheryConfigs {
val sys = Module(LazyModule(new E300ArtyDevKitSystem).module)
val io = new E300ArtyDevKitTopIO
// This needs to be de-asserted synchronously to the coreClk.
val async_corerst = sys.io.aon.rsts.corerst
sys.reset := ResetCatchAndSync(clock, async_corerst, 20)
// ------------------------------------------------------------
// Check for unsupported RCT Connections
// ------------------------------------------------------------
require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported");
// ------------------------------------------------------------
// Build GPIO Pin Mux
// ------------------------------------------------------------
// Pin Mux for UART, SPI, PWM
// First convert the System outputs into "IOF" using the respective *GPIOPort
// converters.
val sys_uarts = sys.io.uarts
val sys_pwms = sys.io.pwms
val sys_spis = sys.io.spis
val uart_pins = uartConfigs.map { c => Module (new UARTGPIOPort) }
val pwm_pins = pwmConfigs.map { c => Module (new PWMGPIOPort(c.bc)) }
val spi_pins = spiConfigs.map { c => Module (new SPIGPIOPort(c)) }
(uart_pins zip sys_uarts) map {case (p, r) => p.io.uart <> r}
(pwm_pins zip sys_pwms) map {case (p, r) => p.io.pwm <> r}
(spi_pins zip sys_spis) map {case (p, r) => p.io.spi <> r}
// ------------------------------------------------------------
// Default Pin connections before attaching pinmux
for (iof_0 <- sys.io.gpio.iof_0) {
iof_0.o := GPIOPinIOFCtrl()
}
for (iof_1 <- sys.io.gpio.iof_1) {
iof_1.o := GPIOPinIOFCtrl()
}
// ------------------------------------------------------------
// TODO: Make this mapping more programmatic.
val iof_0 = sys.io.gpio.iof_0
val iof_1 = sys.io.gpio.iof_1
// SPI1 (0 is the dedicated)
GPIOPinToIOF(spi_pins(0).io.pins.cs(0), iof_0(2))
GPIOPinToIOF(spi_pins(0).io.pins.dq(0), iof_0(3))
GPIOPinToIOF(spi_pins(0).io.pins.dq(1), iof_0(4))
GPIOPinToIOF(spi_pins(0).io.pins.sck, iof_0(5))
GPIOPinToIOF(spi_pins(0).io.pins.dq(2), iof_0(6))
GPIOPinToIOF(spi_pins(0).io.pins.dq(3), iof_0(7))
GPIOPinToIOF(spi_pins(0).io.pins.cs(1), iof_0(8))
GPIOPinToIOF(spi_pins(0).io.pins.cs(2), iof_0(9))
GPIOPinToIOF(spi_pins(0).io.pins.cs(3), iof_0(10))
// SPI2
GPIOPinToIOF(spi_pins(1).io.pins.cs(0), iof_0(26))
GPIOPinToIOF(spi_pins(1).io.pins.dq(0), iof_0(27))
GPIOPinToIOF(spi_pins(1).io.pins.dq(1), iof_0(28))
GPIOPinToIOF(spi_pins(1).io.pins.sck, iof_0(29))
GPIOPinToIOF(spi_pins(1).io.pins.dq(2), iof_0(30))
GPIOPinToIOF(spi_pins(1).io.pins.dq(3), iof_0(31))
// UART0
GPIOPinToIOF(uart_pins(0).io.pins.rxd, iof_0(16))
GPIOPinToIOF(uart_pins(0).io.pins.txd, iof_0(17))
// UART1
GPIOPinToIOF(uart_pins(1).io.pins.rxd, iof_0(24))
GPIOPinToIOF(uart_pins(1).io.pins.txd, iof_0(25))
//PWM
GPIOPinToIOF(pwm_pins(0).io.pins.pwm(0), iof_1(0) )
GPIOPinToIOF(pwm_pins(0).io.pins.pwm(1), iof_1(1) )
GPIOPinToIOF(pwm_pins(0).io.pins.pwm(2), iof_1(2) )
GPIOPinToIOF(pwm_pins(0).io.pins.pwm(3), iof_1(3) )
GPIOPinToIOF(pwm_pins(1).io.pins.pwm(1), iof_1(19))
GPIOPinToIOF(pwm_pins(1).io.pins.pwm(0), iof_1(20))
GPIOPinToIOF(pwm_pins(1).io.pins.pwm(2), iof_1(21))
GPIOPinToIOF(pwm_pins(1).io.pins.pwm(3), iof_1(22))
GPIOPinToIOF(pwm_pins(2).io.pins.pwm(0), iof_1(10))
GPIOPinToIOF(pwm_pins(2).io.pins.pwm(1), iof_1(11))
GPIOPinToIOF(pwm_pins(2).io.pins.pwm(2), iof_1(12))
GPIOPinToIOF(pwm_pins(2).io.pins.pwm(3), iof_1(13))
// ------------------------------------------------------------
// Drive actual Pads
// ------------------------------------------------------------
// Result of Pin Mux
io.pads.gpio <> sys.io.gpio.pins
val dedicated_spi_pins = Module (new SPIGPIOPort(spiFlashConfig, syncStages=3, driveStrength=Bool(true)))
dedicated_spi_pins.clock := sys.clock
dedicated_spi_pins.reset := sys.reset
io.pads.qspi <> dedicated_spi_pins.io.pins
dedicated_spi_pins.io.spi <> sys.io.qspi
// JTAG Debug Interface
val jtag_pins = Module (new JTAGGPIOPort(true))
io.pads.jtag <> jtag_pins.io.pins
sys.io.jtag.get <> jtag_pins.io.jtag
// Override TRST to reset this logic IFF the core is in reset.
// This will require 3 ticks of TCK before the debug logic
// comes out of reset, but JTAG needs 5 ticks anyway.
// This means that the "real" TRST is never actually used in this design.
sys.io.jtag.get.TRST := ResetCatchAndSync(sys.io.jtag.get.TCK, async_corerst)
// AON Pads
io.pads.aon <> sys.io.aon.pads
}

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src/main/scala/unleashed/u500vc707devkit/Configs.scala Normal file
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// See LICENSE for license details.
package sifive.freedom.unleashed.u500vc707devkit
import config._
import coreplex.{WithL1DCacheWays, WithSmallCores, WithoutFPU, BootROMFile}
import rocketchip.{BaseConfig,WithRTCPeriod,WithJtagDTM}
// Don't use directly. Requires additional bootfile configuration
class DefaultFreedomUConfig extends Config(
new WithJtagDTM ++ new BaseConfig
)
class WithBootROMFile(bootROMFile: String) extends Config(
(pname, site, here) => pname match {
case BootROMFile => bootROMFile
case _ => throw new CDEMatchError
}
)
//----------------------------------------------------------------------------------
// Freedom U500 VC707 Dev Kit
class U500VC707DevKitConfig extends Config(
new WithBootROMFile("./bootrom/u500vc707devkit.img") ++
new WithRTCPeriod(62) ++ //Default value of 100 generates 1 Mhz clock @ 100Mhz, then corrected in sbi_entry.c
//Value 62 generates ~ 1Mhz clock @ 62.5Mhz
new WithoutFPU ++
new DefaultFreedomUConfig)

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src/main/scala/unleashed/u500vc707devkit/Top.scala Normal file
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// See LICENSE for license details.
package sifive.freedom.unleashed.u500vc707devkit
import Chisel._
import config._
import util._
import junctions._
import diplomacy._
import uncore.tilelink._
import uncore.devices._
import uncore.util._
import uncore.converters._
import rocket._
import coreplex._
import rocketchip._
import sifive.blocks.devices.xilinxvc707mig._
import sifive.blocks.devices.xilinxvc707pciex1._
import sifive.blocks.devices.gpio.{GPIOConfig, PeripheryGPIO, PeripheryGPIOBundle, PeripheryGPIOModule}
import sifive.blocks.devices.spi.{SPIConfig, PeripherySPI, PeripherySPIBundle, PeripherySPIModule}
import sifive.blocks.devices.uart._
import sifive.blocks.util.ResetCatchAndSync
trait PeripheryConfigs {
val uartConfigs = List(UARTConfig(address = BigInt(0x54000000L)))
val spiConfigs = List(SPIConfig(rAddress = BigInt(0x54001000L)))
val gpioConfig = GPIOConfig(address = BigInt(0x54002000L), width = 4)
}
class U500VC707DevKitSystem(implicit p: Parameters) extends BaseTop
with PeripheryConfigs
with PeripheryBootROM
with PeripheryDebug
with PeripheryCounter
with PeripheryUART
with PeripherySPI
with PeripheryGPIO
with PeripheryXilinxVC707MIG
with PeripheryXilinxVC707PCIeX1
with HardwiredResetVector
with RocketPlexMaster {
override lazy val module = new U500VC707DevKitSystemModule(this, () => new U500VC707DevKitSystemBundle(this))
// scalastyle:off method.length
ConfigStringOutput.contents = Some {
"""platform {
| vendor ucb;
| arch spike;
|};
|plic {
| interface "plic";
| ndevs 9;
| priority { mem { 0x0c000000 0x0c00ffff; }; };
| pending { mem { 0x0c001000 0x0c00107f; }; };
| 0 {
| 0 {
| m {
| ie { mem { 0x0c002000 0x0c00207f; }; };
| ctl { mem { 0x0c200000 0x0c200007; }; };
| };
| s {
| ie { mem { 0x0c002080 0x0c0020ff; }; };
| ctl { mem { 0x0c201000 0x0c201007; }; };
| };
| };
| };
|};
|pcie {
| interface "xilinx-pcie-rv";
| bus {
| mem { 0x60000000 0x7fffffff; } { 0x200000000 0x3ffffffff; };
| bus { 1 63; };
| };
| bridge {
| mem { 0x50000000 0x53ffffff; };
| bus 0;
| irq 6;
| };
|};
|leds {
| interface "gpio";
| ngpio 4;
| mem { 0x54002000 0x54002003; };
|};
|rtc {
| addr 0x200bff8;
|};
|ram {
| 0 {
| addr 0x80000000;
| size 0x10000000;
| };
|};
|uart {
| addr 0x54000000;
|};
|core {
| 0 {
| 0 {
| isa rv64ima;
| timecmp 0x02004000;
| ipi 0x02000000;
| };
| };
|};
|\u0000""".stripMargin
}
// scalastyle:on method.length
}
class U500VC707DevKitSystemBundle[+L <: U500VC707DevKitSystem](_outer: L) extends BaseTopBundle(_outer)
with PeripheryConfigs
with PeripheryBootROMBundle
with PeripheryDebugBundle
with PeripheryCounterBundle
with PeripheryUARTBundle
with PeripherySPIBundle
with PeripheryGPIOBundle
with PeripheryXilinxVC707MIGBundle
with PeripheryXilinxVC707PCIeX1Bundle
with HardwiredResetVectorBundle
with RocketPlexMasterBundle
class U500VC707DevKitSystemModule[+L <: U500VC707DevKitSystem, +B <: U500VC707DevKitSystemBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
with PeripheryConfigs
with PeripheryBootROMModule
with PeripheryDebugModule
with PeripheryCounterModule
with PeripheryUARTModule
with PeripherySPIModule
with PeripheryGPIOModule
with PeripheryXilinxVC707MIGModule
with PeripheryXilinxVC707PCIeX1Module
with HardwiredResetVectorModule
with RocketPlexMasterModule
/////
class ResetDone extends Module {
//unused - in future io.resetdone can set rocketchip STOP_COND/PRINTF_COND
val io = new Bundle{
val reset = Bool(INPUT)
val resetdone = Bool(OUTPUT)
}
val resetdonereg = Reg(init = Bool(false))
val resetff = Reg(init = Bool(false))
resetff := io.reset;
resetdonereg := Mux( ((!io.reset)&&resetff), UInt("b1"), resetdonereg)
io.resetdone := resetdonereg
}
/////
class U500VC707DevKitIO(implicit val p: Parameters) extends Bundle
with PeripheryConfigs
with PeripheryUARTBundle
with PeripherySPIBundle
with PeripheryGPIOBundle
{
val debug = (!p(IncludeJtagDTM)).option(new DebugBusIO()(p).flip)
val jtag = p(IncludeJtagDTM).option(new JTAGIO(true).flip)
//MIG
val xilinxvc707mig = new XilinxVC707MIGPads
//PCIe
val xilinxvc707pcie = new XilinxVC707PCIeX1Pads
//Clocks
val sys_clk_n = Bool(INPUT)
val sys_clk_p = Bool(INPUT)
val pcie_refclk_p = Bool(INPUT)
val pcie_refclk_n = Bool(INPUT)
//Reset
val sys_reset = Bool(INPUT)
//Misc outputs used in system.v
val core_reset = Bool(OUTPUT)
val core_clock = Clock(OUTPUT)
}
/////
class U500VC707DevKitTop(implicit val p: Parameters) extends Module {
// ------------------------------------------------------------
// Instantiate U500 VC707 Dev Kit system (sys)
// ------------------------------------------------------------
val sys = Module(LazyModule(new U500VC707DevKitSystem).module)
val io = new U500VC707DevKitIO
// ------------------------------------------------------------
// Clock and Reset
// ------------------------------------------------------------
val mig_mmcm_locked = Wire(Bool())
val mig_sys_reset = Wire(Bool())
val init_calib_complete = Wire(Bool())
val mmcm_lock_pcie = Wire(Bool())
val do_reset = Wire(Bool())
val mig_clock = Wire(Clock())
val mig_resetn = Wire(Bool())
val top_resetn = Wire(Bool())
val pcie_dat_reset = Wire(Bool())
val pcie_dat_resetn = Wire(Bool())
val pcie_cfg_reset = Wire(Bool())
val pcie_cfg_resetn = Wire(Bool())
val pcie_dat_clock = Wire(Clock())
val pcie_cfg_clock = Wire(Clock())
val top_clock = Wire(Clock())
val top_reset = Wire(Bool())
val mig_reset = Wire(Bool())
do_reset := !mig_mmcm_locked || !mmcm_lock_pcie || mig_sys_reset
mig_resetn := !mig_reset
top_resetn := !top_reset
pcie_dat_resetn := !pcie_dat_reset
pcie_cfg_resetn := !pcie_cfg_reset
// For now, run the CPU synchronous to the PCIe data bus
top_clock := pcie_dat_clock
val safe_reset = Module(new vc707reset)
safe_reset.io.areset := do_reset
safe_reset.io.clock1 := mig_clock
mig_reset := safe_reset.io.reset1
safe_reset.io.clock2 := pcie_dat_clock
pcie_dat_reset := safe_reset.io.reset2
safe_reset.io.clock3 := pcie_cfg_clock
pcie_cfg_reset := safe_reset.io.reset3
safe_reset.io.clock4 := top_clock
top_reset := safe_reset.io.reset4
sys.clock := top_clock
sys.reset := top_reset
// ------------------------------------------------------------
// UART
// ------------------------------------------------------------
io.uarts <> sys.io.uarts
// ------------------------------------------------------------
// SPI
// ------------------------------------------------------------
io.spis <> sys.io.spis
// ------------------------------------------------------------
// GPIO
// ------------------------------------------------------------
io.gpio <> sys.io.gpio
// ------------------------------------------------------------
// MIG
// ------------------------------------------------------------
sys.io.xilinxvc707mig.sys_clk_p := io.sys_clk_p
sys.io.xilinxvc707mig.sys_clk_n := io.sys_clk_n
mig_clock := sys.io.xilinxvc707mig.ui_clk
mig_sys_reset := sys.io.xilinxvc707mig.ui_clk_sync_rst
mig_mmcm_locked := sys.io.xilinxvc707mig.mmcm_locked
sys.io.xilinxvc707mig.aresetn := mig_resetn
init_calib_complete := sys.io.xilinxvc707mig.init_calib_complete
sys.io.xilinxvc707mig.sys_rst := io.sys_reset
//the below bundle assignment is dangerous and relies on matching signal names
// io.xilinxvc707 is of type XilinxVC707MIGPads
// sys.io.xilinxvc707mig is of type XilinxVC707MIGIO
io.xilinxvc707mig <> sys.io.xilinxvc707mig
// ------------------------------------------------------------
// PCIe
// ------------------------------------------------------------
sys.io.xilinxvc707pcie.axi_aresetn := pcie_dat_resetn
pcie_dat_clock := sys.io.xilinxvc707pcie.axi_aclk_out
pcie_cfg_clock := sys.io.xilinxvc707pcie.axi_ctl_aclk_out
mmcm_lock_pcie := sys.io.xilinxvc707pcie.mmcm_lock
sys.io.xilinxvc707pcie.axi_ctl_aresetn := pcie_dat_resetn
sys.io.xilinxvc707pcie.REFCLK_rxp := io.pcie_refclk_p
sys.io.xilinxvc707pcie.REFCLK_rxn := io.pcie_refclk_n
//another dangerous bundle assignment which relies on matching signal names
// io.xilinxvc707pcie is of type XilinxVC707PCIeX1Pads
// sys.io.xilinxvc707pcie is of type XilinxVC707PCIeX1IO
io.xilinxvc707pcie <> sys.io.xilinxvc707pcie
// ------------------------------------------------------------
// Debug
// ------------------------------------------------------------
if (p(IncludeJtagDTM)) {
sys.io.jtag.get <> io.jtag.get
//Override TRST to reset this logic IFF the core is in reset.
// This will require 3 ticks of TCK before the debug logic
// comes out of reset, but JTAG needs 5 ticks anyway.
// This means that the "real" TRST is never actually used.
sys.io.jtag.get.TRST := ResetCatchAndSync(sys.io.jtag.get.TCK, top_reset)
}else{
// SimDTM; only for simulation use
sys.io.debug.get := io.debug.get
// test_mode_clk shouldn't be used for simulation
//sys.io.test_mode_clk := Bool(false).asClock
}
// ------------------------------------------------------------
// Misc outputs used in system.v
// ------------------------------------------------------------
io.core_clock := top_clock
io.core_reset := top_reset
}

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src/main/scala/unleashed/u500vc707devkit/vc707reset.scala Normal file
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// See LICENSE for license details.
package sifive.freedom.unleashed.u500vc707devkit
import Chisel._
//scalastyle:off
//turn off linter: blackbox name must match verilog module
class vc707reset() extends BlackBox
{
val io = new Bundle{
val areset = Bool(INPUT)
val clock1 = Clock(INPUT)
val reset1 = Bool(OUTPUT)
val clock2 = Clock(INPUT)
val reset2 = Bool(OUTPUT)
val clock3 = Clock(INPUT)
val reset3 = Bool(OUTPUT)
val clock4 = Clock(INPUT)
val reset4 = Bool(OUTPUT)
}
}
//scalastyle:on