Initial commit.
This commit is contained in:
SiFive
5
fpga/u500vc707devkit/script/board.tcl
Normal file
5
fpga/u500vc707devkit/script/board.tcl
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@ -0,0 +1,5 @@
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# See LICENSE for license details.
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set name {vc707}
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set part_fpga {xc7vx485tffg1761-2}
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set part_board {xilinx.com:vc707:part0:1.3}
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set bootrom_inst {rom}
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10
fpga/u500vc707devkit/script/cfgmem.tcl
Normal file
10
fpga/u500vc707devkit/script/cfgmem.tcl
Normal file
@ -0,0 +1,10 @@
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lassign $argv mcsfile bitfile datafile
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set iface bpix16
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set size 128
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set bitaddr 0x3000000
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write_cfgmem -format mcs -interface $iface -size $size \
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-loadbit "up ${bitaddr} ${bitfile}" \
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-loaddata [expr {$datafile ne "" ? "up 0x400000 ${datafile}" : ""}] \
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-file $mcsfile -force
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53
fpga/u500vc707devkit/script/impl.tcl
Normal file
53
fpga/u500vc707devkit/script/impl.tcl
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@ -0,0 +1,53 @@
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set_param {messaging.defaultLimit} 1000000
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read_ip [glob -directory $ipdir [file join * {*.xci}]]
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synth_design -top $top -flatten_hierarchy rebuilt
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write_checkpoint -force [file join $wrkdir post_synth]
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opt_design
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write_checkpoint -force [file join $wrkdir post_opt]
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place_design
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write_checkpoint -force [file join $wrkdir post_place]
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phys_opt_design
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power_opt_design
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route_design
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write_checkpoint -force [file join $wrkdir post_route]
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write_bitstream -force [file join $wrkdir "${top}.bit"]
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write_sdf -force [file join $wrkdir "${top}.sdf"]
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write_verilog -mode timesim -force [file join ${wrkdir} "${top}.v"]
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write_debug_probes -force [file join $wrkdir "${top}.ltx"]
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# AR 63042 <http://www.xilinx.com/support/answers/63041.html>:
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# Work around the write_mem_info command not supporting "processor-less"
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# (non-Microblaze) designs.
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set bram_inst [get_cells -hierarchical "bram"]
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if {$bram_inst ne ""} {
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source [file join $scriptdir "bram.tcl"]
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write_mmi [file join $wrkdir "${top}.mmi"] $bram_inst
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}
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if {[info exists bootrom_inst]} {
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puts "Generating bootrom.mmi ..."
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set rom_inst [get_cells -hierarchical "${bootrom_inst}"]
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if {$rom_inst ne ""} {
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source [file join $scriptdir "bram.tcl"]
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write_mmi [file join $wrkdir "bootrom.mmi"] $rom_inst
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}
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}
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set rptdir [file join $wrkdir report]
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file mkdir $rptdir
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set rptutil [file join $rptdir utilization.txt]
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report_datasheet -file [file join $rptdir datasheet.txt]
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report_utilization -hierarchical -file $rptutil
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report_clock_utilization -file $rptutil -append
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report_ram_utilization -file $rptutil -append -detail
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report_timing_summary -file [file join $rptdir timing.txt] -max_paths 10
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report_high_fanout_nets -file [file join $rptdir fanout.txt] -timing -load_types -max_nets 25
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report_drc -file [file join $rptdir drc.txt]
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report_io -file [file join $rptdir io.txt]
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report_clocks -file [file join $rptdir clocks.txt]
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41
fpga/u500vc707devkit/script/init.tcl
Normal file
41
fpga/u500vc707devkit/script/init.tcl
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@ -0,0 +1,41 @@
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proc recglob { basedir pattern } {
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set dirlist [glob -nocomplain -directory $basedir -type d *]
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set findlist [glob -nocomplain -directory $basedir $pattern]
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foreach dir $dirlist {
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set reclist [recglob $dir $pattern]
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set findlist [concat $findlist $reclist]
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}
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return $findlist
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}
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proc findincludedir { basedir pattern } {
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#find all subdirectories containing ".vh" files
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set vhfiles [recglob $basedir $pattern]
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set vhdirs {}
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foreach match $vhfiles {
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lappend vhdirs [file dir $match]
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}
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set uniquevhdirs [lsort -unique $vhdirs]
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return $uniquevhdirs
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}
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file mkdir $ipdir
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update_ip_catalog -rebuild
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source [file join $scriptdir ip.tcl]
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# AR 58526 <http://www.xilinx.com/support/answers/58526.html>
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set_property GENERATE_SYNTH_CHECKPOINT {false} [get_files -all {*.xci}]
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set obj [get_ips]
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generate_target all $obj
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export_ip_user_files -of_objects $obj -no_script -force
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set obj [current_fileset]
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# Xilinx bug workaround
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# scrape IP tree for directories containing .vh files
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# [get_property include_dirs] misses all IP core subdirectory includes if user has specified -dir flag in create_ip
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set property_include_dirs [get_property include_dirs $obj]
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set ip_include_dirs [concat $property_include_dirs [findincludedir $ipdir "*.vh"]]
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set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.h"]]
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set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.vh"]]
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97
fpga/u500vc707devkit/script/ip.tcl
Normal file
97
fpga/u500vc707devkit/script/ip.tcl
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@ -0,0 +1,97 @@
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#MIG
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create_ip -vendor xilinx.com -library ip -name mig_7series -module_name vc707mig -dir $ipdir -force
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set migprj [file join [pwd] $scriptdir {mig.prj}]
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set_property CONFIG.XML_INPUT_FILE $migprj [get_ips vc707mig]
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puts "SCRIPTDIR $scriptdir"
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#AXI_PCIE
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create_ip -vendor xilinx.com -library ip -version 2.8 -name axi_pcie -module_name vc707axi_to_pcie_x1 -dir $ipdir -force
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set_property -dict [list \
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CONFIG.AXIBAR2PCIEBAR_0 {0x60000000} \
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CONFIG.AXIBAR2PCIEBAR_1 {0x00000000} \
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CONFIG.AXIBAR2PCIEBAR_2 {0x00000000} \
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CONFIG.AXIBAR2PCIEBAR_3 {0x00000000} \
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CONFIG.AXIBAR2PCIEBAR_4 {0x00000000} \
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CONFIG.AXIBAR2PCIEBAR_5 {0x00000000} \
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CONFIG.AXIBAR_0 {0x60000000} \
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CONFIG.AXIBAR_1 {0xFFFFFFFF} \
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CONFIG.AXIBAR_2 {0xFFFFFFFF} \
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CONFIG.AXIBAR_3 {0xFFFFFFFF} \
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CONFIG.AXIBAR_4 {0xFFFFFFFF} \
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CONFIG.AXIBAR_5 {0xFFFFFFFF} \
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CONFIG.AXIBAR_AS_0 {true} \
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CONFIG.AXIBAR_AS_1 {false} \
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CONFIG.AXIBAR_AS_2 {false} \
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CONFIG.AXIBAR_AS_3 {false} \
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CONFIG.AXIBAR_AS_4 {false} \
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CONFIG.AXIBAR_AS_5 {false} \
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CONFIG.AXIBAR_HIGHADDR_0 {0x7FFFFFFF} \
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CONFIG.AXIBAR_HIGHADDR_1 {0x00000000} \
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CONFIG.AXIBAR_HIGHADDR_2 {0x00000000} \
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CONFIG.AXIBAR_HIGHADDR_3 {0x00000000} \
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CONFIG.AXIBAR_HIGHADDR_4 {0x00000000} \
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CONFIG.AXIBAR_HIGHADDR_5 {0x00000000} \
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CONFIG.AXIBAR_NUM {1} \
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CONFIG.BAR0_ENABLED {true} \
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CONFIG.BAR0_SCALE {Gigabytes} \
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CONFIG.BAR0_SIZE {4} \
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CONFIG.BAR0_TYPE {Memory} \
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CONFIG.BAR1_ENABLED {false} \
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CONFIG.BAR1_SCALE {N/A} \
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CONFIG.BAR1_SIZE {8} \
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CONFIG.BAR1_TYPE {N/A} \
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CONFIG.BAR2_ENABLED {false} \
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CONFIG.BAR2_SCALE {N/A} \
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CONFIG.BAR2_SIZE {8} \
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CONFIG.BAR2_TYPE {N/A} \
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CONFIG.BAR_64BIT {true} \
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CONFIG.BASEADDR {0x50000000} \
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CONFIG.BASE_CLASS_MENU {Bridge_device} \
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CONFIG.CLASS_CODE {0x060400} \
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CONFIG.COMP_TIMEOUT {50us} \
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CONFIG.Component_Name {design_1_axi_pcie_1_0} \
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CONFIG.DEVICE_ID {0x7111} \
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CONFIG.ENABLE_CLASS_CODE {true} \
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CONFIG.HIGHADDR {0x53FFFFFF} \
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CONFIG.INCLUDE_BAROFFSET_REG {true} \
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CONFIG.INCLUDE_RC {Root_Port_of_PCI_Express_Root_Complex} \
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CONFIG.INTERRUPT_PIN {false} \
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CONFIG.MAX_LINK_SPEED {2.5_GT/s} \
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CONFIG.MSI_DECODE_ENABLED {true} \
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CONFIG.M_AXI_ADDR_WIDTH {32} \
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CONFIG.M_AXI_DATA_WIDTH {64} \
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CONFIG.NO_OF_LANES {X1} \
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CONFIG.NUM_MSI_REQ {0} \
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CONFIG.PCIEBAR2AXIBAR_0_SEC {1} \
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CONFIG.PCIEBAR2AXIBAR_0 {0x00000000} \
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CONFIG.PCIEBAR2AXIBAR_1 {0xFFFFFFFF} \
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CONFIG.PCIEBAR2AXIBAR_1_SEC {1} \
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CONFIG.PCIEBAR2AXIBAR_2 {0xFFFFFFFF} \
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CONFIG.PCIEBAR2AXIBAR_2_SEC {1} \
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CONFIG.PCIE_BLK_LOCN {X1Y1} \
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CONFIG.PCIE_USE_MODE {GES_and_Production} \
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CONFIG.REF_CLK_FREQ {100_MHz} \
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CONFIG.REV_ID {0x00} \
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CONFIG.SLOT_CLOCK_CONFIG {true} \
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CONFIG.SUBSYSTEM_ID {0x0007} \
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CONFIG.SUBSYSTEM_VENDOR_ID {0x10EE} \
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CONFIG.SUB_CLASS_INTERFACE_MENU {Host_bridge} \
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CONFIG.S_AXI_ADDR_WIDTH {32} \
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CONFIG.S_AXI_DATA_WIDTH {64} \
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CONFIG.S_AXI_ID_WIDTH {4} \
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CONFIG.S_AXI_SUPPORTS_NARROW_BURST {false} \
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CONFIG.VENDOR_ID {0x10EE} \
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CONFIG.XLNX_REF_BOARD {None} \
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CONFIG.axi_aclk_loopback {false} \
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CONFIG.en_ext_ch_gt_drp {false} \
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CONFIG.en_ext_clk {false} \
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CONFIG.en_ext_gt_common {false} \
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CONFIG.en_ext_pipe_interface {false} \
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CONFIG.en_transceiver_status_ports {false} \
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CONFIG.no_slv_err {false} \
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CONFIG.rp_bar_hide {true} \
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CONFIG.shared_logic_in_core {false} ] [get_ips vc707axi_to_pcie_x1]
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202
fpga/u500vc707devkit/script/mig.prj
Normal file
202
fpga/u500vc707devkit/script/mig.prj
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@ -0,0 +1,202 @@
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<?xml version='1.0' encoding='UTF-8'?>
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<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
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<Project NoOfControllers="1" >
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<ModuleName>vc707mig</ModuleName>
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<dci_inouts_inputs>1</dci_inouts_inputs>
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<dci_inputs>1</dci_inputs>
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<Debug_En>OFF</Debug_En>
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<DataDepth_En>1024</DataDepth_En>
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<LowPower_En>ON</LowPower_En>
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<XADC_En>Enabled</XADC_En>
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<TargetFPGA>xc7vx485t-ffg1761/-2</TargetFPGA>
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<Version>3.0</Version>
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<SystemClock>Differential</SystemClock>
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<ReferenceClock>Use System Clock</ReferenceClock>
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<SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
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<BankSelectionFlag>FALSE</BankSelectionFlag>
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<InternalVref>0</InternalVref>
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<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
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<dci_cascade>0</dci_cascade>
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<Controller number="0" >
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<MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>
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<TimePeriod>1250</TimePeriod>
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<VccAuxIO>2.0V</VccAuxIO>
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<PHYRatio>4:1</PHYRatio>
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<InputClkFreq>200</InputClkFreq>
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<UIExtraClocks>0</UIExtraClocks>
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<MMCM_VCO>800</MMCM_VCO>
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<MMCMClkOut0> 1.000</MMCMClkOut0>
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<MMCMClkOut1>1</MMCMClkOut1>
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<MMCMClkOut2>1</MMCMClkOut2>
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<MMCMClkOut3>1</MMCMClkOut3>
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<MMCMClkOut4>1</MMCMClkOut4>
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||||
<DataWidth>64</DataWidth>
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||||
<DeepMemory>1</DeepMemory>
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<DataMask>1</DataMask>
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||||
<ECC>Disabled</ECC>
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||||
<Ordering>Normal</Ordering>
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||||
<CustomPart>FALSE</CustomPart>
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<NewPartName></NewPartName>
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||||
<RowAddress>14</RowAddress>
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<ColAddress>10</ColAddress>
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<BankAddress>3</BankAddress>
|
||||
<MemoryVoltage>1.5V</MemoryVoltage>
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<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
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<PinSelection>
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<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A20" SLEW="FAST" name="ddr3_addr[0]" IN_TERM="" />
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||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B21" SLEW="FAST" name="ddr3_addr[10]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B17" SLEW="FAST" name="ddr3_addr[11]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A15" SLEW="FAST" name="ddr3_addr[12]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A21" SLEW="FAST" name="ddr3_addr[13]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B19" SLEW="FAST" name="ddr3_addr[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C20" SLEW="FAST" name="ddr3_addr[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A19" SLEW="FAST" name="ddr3_addr[3]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A17" SLEW="FAST" name="ddr3_addr[4]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A16" SLEW="FAST" name="ddr3_addr[5]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D20" SLEW="FAST" name="ddr3_addr[6]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C18" SLEW="FAST" name="ddr3_addr[7]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D17" SLEW="FAST" name="ddr3_addr[8]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C19" SLEW="FAST" name="ddr3_addr[9]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D21" SLEW="FAST" name="ddr3_ba[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C21" SLEW="FAST" name="ddr3_ba[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D18" SLEW="FAST" name="ddr3_ba[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K17" SLEW="FAST" name="ddr3_cas_n" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="G18" SLEW="FAST" name="ddr3_ck_n[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="H19" SLEW="FAST" name="ddr3_ck_p[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K19" SLEW="FAST" name="ddr3_cke[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="J17" SLEW="FAST" name="ddr3_cs_n[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="M13" SLEW="FAST" name="ddr3_dm[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K15" SLEW="FAST" name="ddr3_dm[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F12" SLEW="FAST" name="ddr3_dm[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A14" SLEW="FAST" name="ddr3_dm[3]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C23" SLEW="FAST" name="ddr3_dm[4]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D25" SLEW="FAST" name="ddr3_dm[5]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C31" SLEW="FAST" name="ddr3_dm[6]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F31" SLEW="FAST" name="ddr3_dm[7]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N14" SLEW="FAST" name="ddr3_dq[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H13" SLEW="FAST" name="ddr3_dq[10]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J13" SLEW="FAST" name="ddr3_dq[11]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L16" SLEW="FAST" name="ddr3_dq[12]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L15" SLEW="FAST" name="ddr3_dq[13]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H14" SLEW="FAST" name="ddr3_dq[14]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J15" SLEW="FAST" name="ddr3_dq[15]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="FAST" name="ddr3_dq[16]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="FAST" name="ddr3_dq[17]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="FAST" name="ddr3_dq[18]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E14" SLEW="FAST" name="ddr3_dq[19]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N13" SLEW="FAST" name="ddr3_dq[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G13" SLEW="FAST" name="ddr3_dq[20]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G12" SLEW="FAST" name="ddr3_dq[21]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="FAST" name="ddr3_dq[22]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G14" SLEW="FAST" name="ddr3_dq[23]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="FAST" name="ddr3_dq[24]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C13" SLEW="FAST" name="ddr3_dq[25]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B16" SLEW="FAST" name="ddr3_dq[26]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="FAST" name="ddr3_dq[27]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="FAST" name="ddr3_dq[28]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="FAST" name="ddr3_dq[29]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L14" SLEW="FAST" name="ddr3_dq[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C16" SLEW="FAST" name="ddr3_dq[30]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="FAST" name="ddr3_dq[31]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A24" SLEW="FAST" name="ddr3_dq[32]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B23" SLEW="FAST" name="ddr3_dq[33]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B27" SLEW="FAST" name="ddr3_dq[34]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B26" SLEW="FAST" name="ddr3_dq[35]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A22" SLEW="FAST" name="ddr3_dq[36]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B22" SLEW="FAST" name="ddr3_dq[37]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A25" SLEW="FAST" name="ddr3_dq[38]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C24" SLEW="FAST" name="ddr3_dq[39]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M14" SLEW="FAST" name="ddr3_dq[3]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E24" SLEW="FAST" name="ddr3_dq[40]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D23" SLEW="FAST" name="ddr3_dq[41]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D26" SLEW="FAST" name="ddr3_dq[42]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C25" SLEW="FAST" name="ddr3_dq[43]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E23" SLEW="FAST" name="ddr3_dq[44]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D22" SLEW="FAST" name="ddr3_dq[45]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F22" SLEW="FAST" name="ddr3_dq[46]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E22" SLEW="FAST" name="ddr3_dq[47]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A30" SLEW="FAST" name="ddr3_dq[48]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D27" SLEW="FAST" name="ddr3_dq[49]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M12" SLEW="FAST" name="ddr3_dq[4]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A29" SLEW="FAST" name="ddr3_dq[50]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C28" SLEW="FAST" name="ddr3_dq[51]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D28" SLEW="FAST" name="ddr3_dq[52]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B31" SLEW="FAST" name="ddr3_dq[53]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A31" SLEW="FAST" name="ddr3_dq[54]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A32" SLEW="FAST" name="ddr3_dq[55]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E30" SLEW="FAST" name="ddr3_dq[56]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F29" SLEW="FAST" name="ddr3_dq[57]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F30" SLEW="FAST" name="ddr3_dq[58]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F27" SLEW="FAST" name="ddr3_dq[59]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N15" SLEW="FAST" name="ddr3_dq[5]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C30" SLEW="FAST" name="ddr3_dq[60]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E29" SLEW="FAST" name="ddr3_dq[61]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F26" SLEW="FAST" name="ddr3_dq[62]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D30" SLEW="FAST" name="ddr3_dq[63]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M11" SLEW="FAST" name="ddr3_dq[6]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L12" SLEW="FAST" name="ddr3_dq[7]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K14" SLEW="FAST" name="ddr3_dq[8]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K13" SLEW="FAST" name="ddr3_dq[9]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="M16" SLEW="FAST" name="ddr3_dqs_n[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="J12" SLEW="FAST" name="ddr3_dqs_n[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G16" SLEW="FAST" name="ddr3_dqs_n[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C14" SLEW="FAST" name="ddr3_dqs_n[3]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A27" SLEW="FAST" name="ddr3_dqs_n[4]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E25" SLEW="FAST" name="ddr3_dqs_n[5]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B29" SLEW="FAST" name="ddr3_dqs_n[6]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E28" SLEW="FAST" name="ddr3_dqs_n[7]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="N16" SLEW="FAST" name="ddr3_dqs_p[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K12" SLEW="FAST" name="ddr3_dqs_p[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="H16" SLEW="FAST" name="ddr3_dqs_p[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C15" SLEW="FAST" name="ddr3_dqs_p[3]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A26" SLEW="FAST" name="ddr3_dqs_p[4]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F25" SLEW="FAST" name="ddr3_dqs_p[5]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B28" SLEW="FAST" name="ddr3_dqs_p[6]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E27" SLEW="FAST" name="ddr3_dqs_p[7]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="H20" SLEW="FAST" name="ddr3_odt[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="E20" SLEW="FAST" name="ddr3_ras_n" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="C29" SLEW="FAST" name="ddr3_reset_n" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F20" SLEW="FAST" name="ddr3_we_n" IN_TERM="" />
|
||||
</PinSelection>
|
||||
<System_Clock>
|
||||
<Pin PADName="E19/E18(CC_P/N)" Bank="38" name="sys_clk_p/n" />
|
||||
</System_Clock>
|
||||
<System_Control>
|
||||
<Pin PADName="AV40" Bank="15" name="sys_rst" />
|
||||
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
|
||||
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
|
||||
</System_Control>
|
||||
<TimingParameters>
|
||||
<Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.75" tras="35" trcd="13.75" />
|
||||
</TimingParameters>
|
||||
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
|
||||
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
|
||||
<mrCasLatency name="CAS Latency" >11</mrCasLatency>
|
||||
<mrMode name="Mode" >Normal</mrMode>
|
||||
<mrDllReset name="DLL Reset" >No</mrDllReset>
|
||||
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
|
||||
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
|
||||
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
|
||||
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
|
||||
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
|
||||
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
|
||||
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
|
||||
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
|
||||
<emrDQS name="TDQS enable" >Enabled</emrDQS>
|
||||
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
|
||||
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
|
||||
<mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>
|
||||
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
|
||||
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
|
||||
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
|
||||
<PortInterface>AXI</PortInterface>
|
||||
<AXIParameters>
|
||||
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
|
||||
<C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
|
||||
<C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
|
||||
<C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
|
||||
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
|
||||
</AXIParameters>
|
||||
</Controller>
|
||||
|
||||
</Project>
|
||||
74
fpga/u500vc707devkit/script/prologue.tcl
Normal file
74
fpga/u500vc707devkit/script/prologue.tcl
Normal file
@ -0,0 +1,74 @@
|
||||
set scriptdir [file dirname [info script]]
|
||||
set commondir [file dirname $scriptdir]
|
||||
set srcdir [file join $commondir src]
|
||||
set constrsdir [file join $commondir constrs]
|
||||
|
||||
set wrkdir [file join [pwd] obj]
|
||||
set ipdir [file join $wrkdir ip]
|
||||
|
||||
set top {system}
|
||||
|
||||
create_project -part $part_fpga -in_memory
|
||||
set_property -dict [list \
|
||||
BOARD_PART $part_board \
|
||||
TARGET_LANGUAGE {Verilog} \
|
||||
SIMULATOR_LANGUAGE {Mixed} \
|
||||
TARGET_SIMULATOR {XSim} \
|
||||
DEFAULT_LIB {xil_defaultlib} \
|
||||
IP_REPO_PATHS $ipdir \
|
||||
] [current_project]
|
||||
|
||||
proc recglob { basedir pattern } {
|
||||
set dirlist [glob -nocomplain -directory $basedir -type d *]
|
||||
set findlist [glob -nocomplain -directory $basedir $pattern]
|
||||
foreach dir $dirlist {
|
||||
set reclist [recglob $dir $pattern]
|
||||
set findlist [concat $findlist $reclist]
|
||||
}
|
||||
return $findlist
|
||||
}
|
||||
|
||||
|
||||
if {[get_filesets -quiet sources_1] eq ""} {
|
||||
create_fileset -srcset sources_1
|
||||
}
|
||||
set obj [current_fileset]
|
||||
|
||||
set srcmainverilogfiles [recglob $srcdir "*.v"]
|
||||
add_files -norecurse -fileset $obj $srcmainverilogfiles
|
||||
|
||||
if {[info exists ::env(EXTRA_VSRCS)]} {
|
||||
set extra_vsrcs [split $::env(EXTRA_VSRCS)]
|
||||
foreach extra_vsrc $extra_vsrcs {
|
||||
add_files -norecurse -fileset $obj $extra_vsrc
|
||||
}
|
||||
}
|
||||
## TODO: These paths and files should come from the caller, not within this script.
|
||||
#if {[file exists [file join $srcdir include verilog]]} {
|
||||
# add_files -norecurse -fileset $obj [file join $srcdir include verilog DebugTransportModuleJtag.v]
|
||||
# add_files -norecurse -fileset $obj [file join $srcdir include verilog AsyncResetReg.v]
|
||||
#}
|
||||
|
||||
set vsrc_top $::env(VSRC_TOP)
|
||||
set vsrc_consts $::env(VSRC_CONSTS)
|
||||
|
||||
set_property verilog_define [list \
|
||||
"VSRC_CONSTS=${vsrc_consts}" \
|
||||
"VSRC_TOP=${vsrc_top}" \
|
||||
] $obj
|
||||
|
||||
add_files -norecurse -fileset $obj $vsrc_top
|
||||
add_files -norecurse -fileset $obj $vsrc_consts
|
||||
|
||||
if {[get_filesets -quiet sim_1] eq ""} {
|
||||
create_fileset -simset sim_1
|
||||
}
|
||||
set obj [current_fileset -simset]
|
||||
add_files -norecurse -fileset $obj [glob -directory $srcdir {*.v}]
|
||||
set_property TOP {tb} $obj
|
||||
|
||||
if {[get_filesets -quiet constrs_1] eq ""} {
|
||||
create_fileset -constrset constrs_1
|
||||
}
|
||||
set obj [current_fileset -constrset]
|
||||
add_files -norecurse -fileset $obj [glob -directory $constrsdir {*.xdc}]
|
||||
Reference in New Issue
Block a user