Initial commit.

fpga/e300artydevkit/script/board.tcl

@@ -0,0 +1,4 @@
+set name {arty_e300devkit}
+set part_fpga {xc7a35ticsg324-1L}
+set part_board {digilentinc.com:arty:part0:1.1}
+set bootrom_inst {rom}

fpga/e300artydevkit/script/cfgmem.tcl

@@ -0,0 +1,10 @@
+lassign $argv mcsfile bitfile datafile
+
+set iface spix4
+set size 16
+set bitaddr 0x0
+
+write_cfgmem -format mcs -interface $iface -size $size \
+  -loadbit "up ${bitaddr} ${bitfile}" \
+  -loaddata [expr {$datafile ne "" ? "up 0x400000 ${datafile}" : ""}] \
+  -file $mcsfile -force

fpga/e300artydevkit/script/impl.tcl

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+set_param {messaging.defaultLimit} 1000000
+
+read_ip [glob -directory $ipdir [file join * {*.xci}]]
+
+synth_design -top $top -flatten_hierarchy rebuilt
+write_checkpoint -force [file join $wrkdir post_synth]
+
+opt_design
+write_checkpoint -force [file join $wrkdir post_opt]
+
+place_design
+write_checkpoint -force [file join $wrkdir post_place]
+
+phys_opt_design
+power_opt_design
+route_design
+write_checkpoint -force [file join $wrkdir post_route]
+
+write_bitstream -force [file join $wrkdir "${top}.bit"]
+write_sdf -force [file join $wrkdir "${top}.sdf"]
+write_verilog -mode timesim -force [file join ${wrkdir} "${top}.v"]
+write_debug_probes -force [file join $wrkdir "${top}.ltx"]
+
+# AR 63042 <http://www.xilinx.com/support/answers/63041.html>:
+# Work around the write_mem_info command not supporting "processor-less"
+# (non-Microblaze) designs.
+set bram_inst [get_cells -hierarchical "bram"]
+if {$bram_inst ne ""} {
+  source [file join $scriptdir "bram.tcl"]
+  write_mmi [file join $wrkdir "${top}.mmi"] $bram_inst
+}
+
+if {[info exists bootrom_inst]} {
+  puts "Generating bootrom.mmi ..."
+  set rom_inst [get_cells -hierarchical "${bootrom_inst}"]
+  if {$rom_inst ne ""} {
+    source [file join $scriptdir "bram.tcl"]
+    write_mmi [file join $wrkdir "bootrom.mmi"] $rom_inst
+  }
+}
+
+set rptdir [file join $wrkdir report]
+file mkdir $rptdir
+set rptutil [file join $rptdir utilization.txt]
+report_datasheet -file [file join $rptdir datasheet.txt]
+report_utilization -hierarchical -file $rptutil
+report_clock_utilization -file $rptutil -append
+report_ram_utilization -file $rptutil -append -detail
+report_timing_summary -file [file join $rptdir timing.txt] -max_paths 10
+report_high_fanout_nets -file [file join $rptdir fanout.txt] -timing -load_types -max_nets 25
+report_drc -file [file join $rptdir drc.txt]
+report_io -file [file join $rptdir io.txt]
+report_clocks -file [file join $rptdir clocks.txt]

fpga/e300artydevkit/script/init.tcl

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+proc recglob { basedir pattern } {
+  set dirlist [glob -nocomplain -directory $basedir -type d *]
+  set findlist [glob -nocomplain -directory $basedir $pattern]
+  foreach dir $dirlist {
+    set reclist [recglob $dir $pattern]
+    set findlist [concat $findlist $reclist]
+  }
+  return $findlist
+}
+
+proc findincludedir { basedir pattern } {
+  #find all subdirectories containing ".vh" files
+  set vhfiles [recglob $basedir $pattern]
+  set vhdirs {}
+  foreach match $vhfiles {
+    lappend vhdirs [file dir $match]
+  }
+  set uniquevhdirs [lsort -unique $vhdirs]
+  return $uniquevhdirs
+}
+
+file mkdir $ipdir
+update_ip_catalog -rebuild
+
+source [file join $scriptdir ip.tcl]
+
+# AR 58526 <http://www.xilinx.com/support/answers/58526.html>
+set_property GENERATE_SYNTH_CHECKPOINT {false} [get_files -all {*.xci}]
+set obj [get_ips]
+generate_target all $obj
+export_ip_user_files -of_objects $obj -no_script -force
+
+set obj [current_fileset]
+
+# Xilinx bug workaround
+# scrape IP tree for directories containing .vh files
+# [get_property include_dirs] misses all IP core subdirectory includes if user has specified -dir flag in create_ip
+set property_include_dirs [get_property include_dirs $obj]
+set ip_include_dirs [concat $property_include_dirs [findincludedir $ipdir "*.vh"]]
+set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.h"]]
+set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.vh"]]

fpga/e300artydevkit/script/ip.tcl

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+create_ip -vendor xilinx.com -library ip -name clk_wiz -module_name mmcm -dir $ipdir -force
+set_property -dict [list \
+  CONFIG.PRIMITIVE {MMCM} \
+  CONFIG.RESET_TYPE {ACTIVE_LOW} \
+  CONFIG.CLKOUT1_USED {true} \
+  CONFIG.CLKOUT2_USED {true} \
+  CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {8.388} \
+  CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {65.000} \
+  ] [get_ips mmcm]
+
+create_ip -vendor xilinx.com -library ip -name proc_sys_reset -module_name reset_sys -dir $ipdir -force
+set_property -dict [list \
+  CONFIG.C_EXT_RESET_HIGH {false} \
+  CONFIG.C_AUX_RESET_HIGH {false} \
+  CONFIG.C_NUM_BUS_RST {1} \
+  CONFIG.C_NUM_PERP_RST {1} \
+  CONFIG.C_NUM_INTERCONNECT_ARESETN {1} \
+  CONFIG.C_NUM_PERP_ARESETN {1} \
+  ] [get_ips reset_sys]

fpga/e300artydevkit/script/prologue.tcl

@@ -0,0 +1,74 @@
+set scriptdir [file dirname [info script]]
+set commondir [file dirname $scriptdir]
+set srcdir [file join $commondir src]
+set constrsdir [file join $commondir constrs]
+
+set wrkdir [file join [pwd] obj]
+set ipdir [file join $wrkdir ip]
+
+set top {system}
+
+create_project -part $part_fpga -in_memory
+set_property -dict [list \
+  BOARD_PART $part_board \
+  TARGET_LANGUAGE {Verilog} \
+  SIMULATOR_LANGUAGE {Mixed} \
+  TARGET_SIMULATOR {XSim} \
+  DEFAULT_LIB {xil_defaultlib} \
+  IP_REPO_PATHS $ipdir \
+  ] [current_project]
+
+proc recglob { basedir pattern } {
+  set dirlist [glob -nocomplain -directory $basedir -type d *]
+  set findlist [glob -nocomplain -directory $basedir $pattern]
+  foreach dir $dirlist {
+    set reclist [recglob $dir $pattern]
+    set findlist [concat $findlist $reclist]
+  }
+  return $findlist
+}
+
+
+if {[get_filesets -quiet sources_1] eq ""} {
+  create_fileset -srcset sources_1
+}
+set obj [current_fileset]
+
+set srcmainverilogfiles [recglob $srcdir "*.v"]
+add_files -norecurse -fileset $obj $srcmainverilogfiles
+
+if {[info exists ::env(EXTRA_VSRCS)]} {
+  set extra_vsrcs [split $::env(EXTRA_VSRCS)]
+  foreach extra_vsrc $extra_vsrcs {
+    add_files -norecurse -fileset $obj $extra_vsrc
+  }
+}
+## TODO: These paths and files should come from the caller, not within this script.
+#if {[file exists [file join $srcdir include verilog]]} {
+#  add_files -norecurse -fileset $obj [file join $srcdir include verilog DebugTransportModuleJtag.v]
+#  add_files -norecurse -fileset $obj [file join $srcdir include verilog AsyncResetReg.v]
+#}
+
+set vsrc_top $::env(VSRC_TOP)
+set vsrc_consts $::env(VSRC_CONSTS)
+
+set_property verilog_define [list \
+                                 "VSRC_CONSTS=${vsrc_consts}" \
+                                 "VSRC_TOP=${vsrc_top}" \
+                                ] $obj
+
+add_files -norecurse -fileset $obj $vsrc_top
+add_files -norecurse -fileset $obj $vsrc_consts
+
+if {[get_filesets -quiet sim_1] eq ""} {
+  create_fileset -simset sim_1
+}
+set obj [current_fileset -simset]
+add_files -norecurse -fileset $obj [glob -directory $srcdir {*.v}]
+set_property TOP {tb} $obj
+
+if {[get_filesets -quiet constrs_1] eq ""} {
+  create_fileset -constrset constrs_1
+}
+set obj [current_fileset -constrset]
+add_files -norecurse -fileset $obj [glob -directory $constrsdir {*.xdc}]