Initial commit.
This commit is contained in:
SiFive
4
fpga/e300artydevkit/script/board.tcl
Normal file
4
fpga/e300artydevkit/script/board.tcl
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set name {arty_e300devkit}
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set part_fpga {xc7a35ticsg324-1L}
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set part_board {digilentinc.com:arty:part0:1.1}
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set bootrom_inst {rom}
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10
fpga/e300artydevkit/script/cfgmem.tcl
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10
fpga/e300artydevkit/script/cfgmem.tcl
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lassign $argv mcsfile bitfile datafile
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set iface spix4
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set size 16
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set bitaddr 0x0
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write_cfgmem -format mcs -interface $iface -size $size \
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-loadbit "up ${bitaddr} ${bitfile}" \
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-loaddata [expr {$datafile ne "" ? "up 0x400000 ${datafile}" : ""}] \
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-file $mcsfile -force
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53
fpga/e300artydevkit/script/impl.tcl
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53
fpga/e300artydevkit/script/impl.tcl
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set_param {messaging.defaultLimit} 1000000
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read_ip [glob -directory $ipdir [file join * {*.xci}]]
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synth_design -top $top -flatten_hierarchy rebuilt
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write_checkpoint -force [file join $wrkdir post_synth]
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opt_design
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write_checkpoint -force [file join $wrkdir post_opt]
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place_design
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write_checkpoint -force [file join $wrkdir post_place]
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phys_opt_design
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power_opt_design
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route_design
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write_checkpoint -force [file join $wrkdir post_route]
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write_bitstream -force [file join $wrkdir "${top}.bit"]
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write_sdf -force [file join $wrkdir "${top}.sdf"]
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write_verilog -mode timesim -force [file join ${wrkdir} "${top}.v"]
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write_debug_probes -force [file join $wrkdir "${top}.ltx"]
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# AR 63042 <http://www.xilinx.com/support/answers/63041.html>:
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# Work around the write_mem_info command not supporting "processor-less"
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# (non-Microblaze) designs.
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set bram_inst [get_cells -hierarchical "bram"]
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if {$bram_inst ne ""} {
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source [file join $scriptdir "bram.tcl"]
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write_mmi [file join $wrkdir "${top}.mmi"] $bram_inst
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}
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if {[info exists bootrom_inst]} {
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puts "Generating bootrom.mmi ..."
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set rom_inst [get_cells -hierarchical "${bootrom_inst}"]
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if {$rom_inst ne ""} {
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source [file join $scriptdir "bram.tcl"]
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write_mmi [file join $wrkdir "bootrom.mmi"] $rom_inst
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}
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}
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set rptdir [file join $wrkdir report]
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file mkdir $rptdir
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set rptutil [file join $rptdir utilization.txt]
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report_datasheet -file [file join $rptdir datasheet.txt]
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report_utilization -hierarchical -file $rptutil
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report_clock_utilization -file $rptutil -append
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report_ram_utilization -file $rptutil -append -detail
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report_timing_summary -file [file join $rptdir timing.txt] -max_paths 10
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report_high_fanout_nets -file [file join $rptdir fanout.txt] -timing -load_types -max_nets 25
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report_drc -file [file join $rptdir drc.txt]
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report_io -file [file join $rptdir io.txt]
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report_clocks -file [file join $rptdir clocks.txt]
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41
fpga/e300artydevkit/script/init.tcl
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41
fpga/e300artydevkit/script/init.tcl
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proc recglob { basedir pattern } {
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set dirlist [glob -nocomplain -directory $basedir -type d *]
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set findlist [glob -nocomplain -directory $basedir $pattern]
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foreach dir $dirlist {
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set reclist [recglob $dir $pattern]
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set findlist [concat $findlist $reclist]
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}
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return $findlist
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}
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proc findincludedir { basedir pattern } {
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#find all subdirectories containing ".vh" files
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set vhfiles [recglob $basedir $pattern]
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set vhdirs {}
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foreach match $vhfiles {
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lappend vhdirs [file dir $match]
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}
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set uniquevhdirs [lsort -unique $vhdirs]
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return $uniquevhdirs
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}
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file mkdir $ipdir
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update_ip_catalog -rebuild
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source [file join $scriptdir ip.tcl]
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# AR 58526 <http://www.xilinx.com/support/answers/58526.html>
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set_property GENERATE_SYNTH_CHECKPOINT {false} [get_files -all {*.xci}]
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set obj [get_ips]
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generate_target all $obj
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export_ip_user_files -of_objects $obj -no_script -force
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set obj [current_fileset]
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# Xilinx bug workaround
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# scrape IP tree for directories containing .vh files
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# [get_property include_dirs] misses all IP core subdirectory includes if user has specified -dir flag in create_ip
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set property_include_dirs [get_property include_dirs $obj]
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set ip_include_dirs [concat $property_include_dirs [findincludedir $ipdir "*.vh"]]
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set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.h"]]
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set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.vh"]]
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19
fpga/e300artydevkit/script/ip.tcl
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19
fpga/e300artydevkit/script/ip.tcl
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create_ip -vendor xilinx.com -library ip -name clk_wiz -module_name mmcm -dir $ipdir -force
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set_property -dict [list \
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CONFIG.PRIMITIVE {MMCM} \
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CONFIG.RESET_TYPE {ACTIVE_LOW} \
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CONFIG.CLKOUT1_USED {true} \
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CONFIG.CLKOUT2_USED {true} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {8.388} \
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CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {65.000} \
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] [get_ips mmcm]
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create_ip -vendor xilinx.com -library ip -name proc_sys_reset -module_name reset_sys -dir $ipdir -force
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set_property -dict [list \
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CONFIG.C_EXT_RESET_HIGH {false} \
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CONFIG.C_AUX_RESET_HIGH {false} \
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CONFIG.C_NUM_BUS_RST {1} \
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CONFIG.C_NUM_PERP_RST {1} \
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CONFIG.C_NUM_INTERCONNECT_ARESETN {1} \
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CONFIG.C_NUM_PERP_ARESETN {1} \
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] [get_ips reset_sys]
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74
fpga/e300artydevkit/script/prologue.tcl
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74
fpga/e300artydevkit/script/prologue.tcl
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set scriptdir [file dirname [info script]]
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set commondir [file dirname $scriptdir]
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set srcdir [file join $commondir src]
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set constrsdir [file join $commondir constrs]
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set wrkdir [file join [pwd] obj]
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set ipdir [file join $wrkdir ip]
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set top {system}
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create_project -part $part_fpga -in_memory
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set_property -dict [list \
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BOARD_PART $part_board \
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TARGET_LANGUAGE {Verilog} \
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SIMULATOR_LANGUAGE {Mixed} \
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TARGET_SIMULATOR {XSim} \
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DEFAULT_LIB {xil_defaultlib} \
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IP_REPO_PATHS $ipdir \
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] [current_project]
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proc recglob { basedir pattern } {
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set dirlist [glob -nocomplain -directory $basedir -type d *]
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set findlist [glob -nocomplain -directory $basedir $pattern]
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foreach dir $dirlist {
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set reclist [recglob $dir $pattern]
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set findlist [concat $findlist $reclist]
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}
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return $findlist
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}
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if {[get_filesets -quiet sources_1] eq ""} {
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create_fileset -srcset sources_1
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}
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set obj [current_fileset]
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set srcmainverilogfiles [recglob $srcdir "*.v"]
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add_files -norecurse -fileset $obj $srcmainverilogfiles
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if {[info exists ::env(EXTRA_VSRCS)]} {
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set extra_vsrcs [split $::env(EXTRA_VSRCS)]
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foreach extra_vsrc $extra_vsrcs {
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add_files -norecurse -fileset $obj $extra_vsrc
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}
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}
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## TODO: These paths and files should come from the caller, not within this script.
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#if {[file exists [file join $srcdir include verilog]]} {
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# add_files -norecurse -fileset $obj [file join $srcdir include verilog DebugTransportModuleJtag.v]
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# add_files -norecurse -fileset $obj [file join $srcdir include verilog AsyncResetReg.v]
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#}
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set vsrc_top $::env(VSRC_TOP)
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set vsrc_consts $::env(VSRC_CONSTS)
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set_property verilog_define [list \
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"VSRC_CONSTS=${vsrc_consts}" \
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"VSRC_TOP=${vsrc_top}" \
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] $obj
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add_files -norecurse -fileset $obj $vsrc_top
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add_files -norecurse -fileset $obj $vsrc_consts
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if {[get_filesets -quiet sim_1] eq ""} {
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create_fileset -simset sim_1
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}
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set obj [current_fileset -simset]
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add_files -norecurse -fileset $obj [glob -directory $srcdir {*.v}]
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set_property TOP {tb} $obj
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if {[get_filesets -quiet constrs_1] eq ""} {
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create_fileset -constrset constrs_1
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}
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set obj [current_fileset -constrset]
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add_files -norecurse -fileset $obj [glob -directory $constrsdir {*.xdc}]
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