Initial commit.
This commit is contained in:
SiFive
8
fpga/e300artydevkit/.gitignore
vendored
Normal file
8
fpga/e300artydevkit/.gitignore
vendored
Normal file
@ -0,0 +1,8 @@
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.Xil
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.ip_user_files
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*.log
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*.html
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*.xml
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fsm_encoding.os
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obj
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src/generated
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23
fpga/e300artydevkit/Makefile
Normal file
23
fpga/e300artydevkit/Makefile
Normal file
@ -0,0 +1,23 @@
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VIVADO ?= vivado
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VIVADOFLAGS := \
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-nojournal -mode batch \
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-source script/board.tcl \
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-source script/prologue.tcl
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bit := obj/system.bit
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$(bit): script/impl.tcl script/init.tcl
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VSRC_TOP=$(VSRC_TOP) VSRC_CONSTS=$(VSRC_CONSTS) EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source script/init.tcl -source script/impl.tcl
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.PHONY: bit
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bit: $(bit)
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mcs := obj/system.mcs
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$(mcs): $(bit)
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$(VIVADO) $(VIVADOFLAGS) script/cfgmem.tcl -tclargs $@ $^
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.PHONY: mcs
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mcs: $(mcs)
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.PHONY: clean
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clean::
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rm -rf -- .Xil .ip_user_files *.os obj src/generated usage_statistics_webtalk.xml usage_statistics_webtalk.html *.log
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5
fpga/e300artydevkit/constrs/arty-config.xdc
Normal file
5
fpga/e300artydevkit/constrs/arty-config.xdc
Normal file
@ -0,0 +1,5 @@
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set_property -dict [list \
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CONFIG_VOLTAGE {3.3} \
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CFGBVS {VCCO} \
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BITSTREAM.CONFIG.SPI_BUSWIDTH {4} \
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] [current_design]
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230
fpga/e300artydevkit/constrs/arty-master.xdc
Normal file
230
fpga/e300artydevkit/constrs/arty-master.xdc
Normal file
@ -0,0 +1,230 @@
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## This file is a general .xdc for the ARTY Rev. B
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## To use it in a project:
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## - uncomment the lines corresponding to used pins
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## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
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## Clock signal
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set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
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create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
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##Switches
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set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { sw_0 }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
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set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { sw_1 }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
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set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { sw_2 }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
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set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { sw_3 }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
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##RGB LEDs
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set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L18N_T2_35 Sch=led0_b
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set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L19N_T3_VREF_35 Sch=led0_g
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set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L19P_T3_35 Sch=led0_r
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set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L20P_T3_35 Sch=led1_b
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set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L21P_T3_DQS_35 Sch=led1_g
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set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L20N_T3_35 Sch=led1_r
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set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { led2_b }]; #IO_L21N_T3_DQS_35 Sch=led2_b
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set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { led2_g }]; #IO_L22N_T3_35 Sch=led2_g
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set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { led2_r }]; #IO_L22P_T3_35 Sch=led2_r
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#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { led3_b }]; #IO_L23P_T3_35 Sch=led3_b
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#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { led3_g }]; #IO_L24P_T3_35 Sch=led3_g
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#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { led3_r }]; #IO_L23N_T3_35 Sch=led3_r
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##LEDs
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set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { led_0 }]; #IO_L24N_T3_35 Sch=led[4]
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set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { led_1 }]; #IO_25_35 Sch=led[5]
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set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { led_2 }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
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set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { led_3 }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
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##Buttons
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set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { btn_0 }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
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set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn_1 }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
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set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { btn_2 }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
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set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { btn_3 }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
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##Pmod Header JA
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set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja_0 }]; #IO_0_15 Sch=ja[1]
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set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { ja_1 }]; #IO_L4P_T0_15 Sch=ja[2]
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#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { ja_2 }]; #IO_L4N_T0_15 Sch=ja[3]
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#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { ja_3 }]; #IO_L6P_T0_15 Sch=ja[4]
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#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { ja_4 }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
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#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { ja_5 }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
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||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { ja_6 }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
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#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja_7 }]; #IO_25_15 Sch=ja[10]
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||||
##Pmod Header JB
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||||
|
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#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jb_0 }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
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||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb_1 }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
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||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jb_2 }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
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||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { jb_3 }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
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||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { jb_4 }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
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#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { jb_5 }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
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#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { jb_6 }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
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||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { jb_7 }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
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||||
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##Pmod Header JC
|
||||
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
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#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
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#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
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#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
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||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
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||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
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||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
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||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
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||||
|
||||
##Pmod Header JD
|
||||
|
||||
set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { jd_0 }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
|
||||
set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { jd_1 }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
|
||||
set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { jd_2 }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd_3 }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
|
||||
set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { jd_4 }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
|
||||
set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { jd_5 }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
|
||||
set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd_6 }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd_7 }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
|
||||
|
||||
##USB-UART Interface (FTDI FT2232H)
|
||||
|
||||
set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
|
||||
set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
|
||||
|
||||
|
||||
##ChipKit Single Ended Analog Inputs
|
||||
##NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5).
|
||||
## These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins ck_io[14-19].
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0]
|
||||
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0]
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1]
|
||||
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[1] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1]
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[2] }]; #IO_L7N_T1_AD6N_35 Sch=ck_an_n[2]
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[2] }]; #IO_L7P_T1_AD6P_35 Sch=ck_an_p[2]
|
||||
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[3] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3]
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[3] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3]
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[4] }]; #IO_L10N_T1_AD15N_35 Sch=ck_an_n[4]
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[4] }]; #IO_L10P_T1_AD15P_35 Sch=ck_an_p[4]
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[5] }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[5]
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[5] }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[5]
|
||||
|
||||
##ChipKit Digital I/O Low
|
||||
|
||||
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[0] }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
|
||||
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[1] }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
|
||||
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[2] }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
|
||||
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[3] }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
|
||||
set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io[4] }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
|
||||
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[5] }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
|
||||
set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[6] }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
|
||||
set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[7] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
|
||||
set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[8] }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8]
|
||||
set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[9] }]; #IO_L10P_T1_D14_14 Sch=ck_io[9]
|
||||
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[10] }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10]
|
||||
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[11] }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11]
|
||||
set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[12] }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12]
|
||||
set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[13] }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13]
|
||||
|
||||
##ChipKit Digital I/O On Outer Analog Header
|
||||
##NOTE: These pins should be used when using the analog header signals A0-A5 as digital I/O (Chipkit digital pins 14-19)
|
||||
|
||||
set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[14] }]; #IO_0_35 Sch=ck_a[0]
|
||||
set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { ck_io[15] }]; #IO_L4P_T0_35 Sch=ck_a[1]
|
||||
set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[16] }]; #IO_L4N_T0_35 Sch=ck_a[2]
|
||||
set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[17] }]; #IO_L6P_T0_35 Sch=ck_a[3]
|
||||
set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[18] }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4]
|
||||
set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[19] }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5]
|
||||
|
||||
##ChipKit Digital I/O On Inner Analog Header
|
||||
##NOTE: These pins will need to be connected to the XADC core when used as differential analog inputs (Chipkit analog pins A6-A11)
|
||||
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[20] }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12]
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { ck_io[21] }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12]
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { ck_io[22] }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13]
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[23] }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { ck_io[24] }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14]
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { ck_io[25] }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14]
|
||||
|
||||
##ChipKit Digital I/O High
|
||||
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[26] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[27] }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { ck_io[28] }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { ck_io[29] }]; #IO_25_14 Sch=ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[30] }]; #IO_0_14 Sch=ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { ck_io[31] }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[32] }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[33] }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[34] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[35] }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[36] }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[37] }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[38] }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[39] }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[40] }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[41] }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
|
||||
|
||||
## ChipKit SPI
|
||||
|
||||
set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
|
||||
set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
|
||||
set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
|
||||
set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
|
||||
|
||||
## ChipKit I2C
|
||||
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
|
||||
|
||||
##Misc. ChipKit signals
|
||||
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
|
||||
set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst
|
||||
|
||||
##SMSC Ethernet PHY
|
||||
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
|
||||
|
||||
##Quad SPI Flash
|
||||
|
||||
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 IOB TRUE } [get_ports { qspi_sck }];
|
||||
create_clock -add -name qspi_sck_pin -period 20.00 -waveform {0 10} [get_ports { qspi_sck }];
|
||||
set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 IOB TRUE } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 IOB TRUE PULLUP TRUE } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 IOB TRUE PULLUP TRUE } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 IOB TRUE PULLUP TRUE } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 IOB TRUE PULLUP TRUE } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
##Power Measurements
|
||||
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
|
||||
4
fpga/e300artydevkit/script/board.tcl
Normal file
4
fpga/e300artydevkit/script/board.tcl
Normal file
@ -0,0 +1,4 @@
|
||||
set name {arty_e300devkit}
|
||||
set part_fpga {xc7a35ticsg324-1L}
|
||||
set part_board {digilentinc.com:arty:part0:1.1}
|
||||
set bootrom_inst {rom}
|
||||
10
fpga/e300artydevkit/script/cfgmem.tcl
Normal file
10
fpga/e300artydevkit/script/cfgmem.tcl
Normal file
@ -0,0 +1,10 @@
|
||||
lassign $argv mcsfile bitfile datafile
|
||||
|
||||
set iface spix4
|
||||
set size 16
|
||||
set bitaddr 0x0
|
||||
|
||||
write_cfgmem -format mcs -interface $iface -size $size \
|
||||
-loadbit "up ${bitaddr} ${bitfile}" \
|
||||
-loaddata [expr {$datafile ne "" ? "up 0x400000 ${datafile}" : ""}] \
|
||||
-file $mcsfile -force
|
||||
53
fpga/e300artydevkit/script/impl.tcl
Normal file
53
fpga/e300artydevkit/script/impl.tcl
Normal file
@ -0,0 +1,53 @@
|
||||
set_param {messaging.defaultLimit} 1000000
|
||||
|
||||
read_ip [glob -directory $ipdir [file join * {*.xci}]]
|
||||
|
||||
synth_design -top $top -flatten_hierarchy rebuilt
|
||||
write_checkpoint -force [file join $wrkdir post_synth]
|
||||
|
||||
opt_design
|
||||
write_checkpoint -force [file join $wrkdir post_opt]
|
||||
|
||||
place_design
|
||||
write_checkpoint -force [file join $wrkdir post_place]
|
||||
|
||||
phys_opt_design
|
||||
power_opt_design
|
||||
route_design
|
||||
write_checkpoint -force [file join $wrkdir post_route]
|
||||
|
||||
write_bitstream -force [file join $wrkdir "${top}.bit"]
|
||||
write_sdf -force [file join $wrkdir "${top}.sdf"]
|
||||
write_verilog -mode timesim -force [file join ${wrkdir} "${top}.v"]
|
||||
write_debug_probes -force [file join $wrkdir "${top}.ltx"]
|
||||
|
||||
# AR 63042 <http://www.xilinx.com/support/answers/63041.html>:
|
||||
# Work around the write_mem_info command not supporting "processor-less"
|
||||
# (non-Microblaze) designs.
|
||||
set bram_inst [get_cells -hierarchical "bram"]
|
||||
if {$bram_inst ne ""} {
|
||||
source [file join $scriptdir "bram.tcl"]
|
||||
write_mmi [file join $wrkdir "${top}.mmi"] $bram_inst
|
||||
}
|
||||
|
||||
if {[info exists bootrom_inst]} {
|
||||
puts "Generating bootrom.mmi ..."
|
||||
set rom_inst [get_cells -hierarchical "${bootrom_inst}"]
|
||||
if {$rom_inst ne ""} {
|
||||
source [file join $scriptdir "bram.tcl"]
|
||||
write_mmi [file join $wrkdir "bootrom.mmi"] $rom_inst
|
||||
}
|
||||
}
|
||||
|
||||
set rptdir [file join $wrkdir report]
|
||||
file mkdir $rptdir
|
||||
set rptutil [file join $rptdir utilization.txt]
|
||||
report_datasheet -file [file join $rptdir datasheet.txt]
|
||||
report_utilization -hierarchical -file $rptutil
|
||||
report_clock_utilization -file $rptutil -append
|
||||
report_ram_utilization -file $rptutil -append -detail
|
||||
report_timing_summary -file [file join $rptdir timing.txt] -max_paths 10
|
||||
report_high_fanout_nets -file [file join $rptdir fanout.txt] -timing -load_types -max_nets 25
|
||||
report_drc -file [file join $rptdir drc.txt]
|
||||
report_io -file [file join $rptdir io.txt]
|
||||
report_clocks -file [file join $rptdir clocks.txt]
|
||||
41
fpga/e300artydevkit/script/init.tcl
Normal file
41
fpga/e300artydevkit/script/init.tcl
Normal file
@ -0,0 +1,41 @@
|
||||
proc recglob { basedir pattern } {
|
||||
set dirlist [glob -nocomplain -directory $basedir -type d *]
|
||||
set findlist [glob -nocomplain -directory $basedir $pattern]
|
||||
foreach dir $dirlist {
|
||||
set reclist [recglob $dir $pattern]
|
||||
set findlist [concat $findlist $reclist]
|
||||
}
|
||||
return $findlist
|
||||
}
|
||||
|
||||
proc findincludedir { basedir pattern } {
|
||||
#find all subdirectories containing ".vh" files
|
||||
set vhfiles [recglob $basedir $pattern]
|
||||
set vhdirs {}
|
||||
foreach match $vhfiles {
|
||||
lappend vhdirs [file dir $match]
|
||||
}
|
||||
set uniquevhdirs [lsort -unique $vhdirs]
|
||||
return $uniquevhdirs
|
||||
}
|
||||
|
||||
file mkdir $ipdir
|
||||
update_ip_catalog -rebuild
|
||||
|
||||
source [file join $scriptdir ip.tcl]
|
||||
|
||||
# AR 58526 <http://www.xilinx.com/support/answers/58526.html>
|
||||
set_property GENERATE_SYNTH_CHECKPOINT {false} [get_files -all {*.xci}]
|
||||
set obj [get_ips]
|
||||
generate_target all $obj
|
||||
export_ip_user_files -of_objects $obj -no_script -force
|
||||
|
||||
set obj [current_fileset]
|
||||
|
||||
# Xilinx bug workaround
|
||||
# scrape IP tree for directories containing .vh files
|
||||
# [get_property include_dirs] misses all IP core subdirectory includes if user has specified -dir flag in create_ip
|
||||
set property_include_dirs [get_property include_dirs $obj]
|
||||
set ip_include_dirs [concat $property_include_dirs [findincludedir $ipdir "*.vh"]]
|
||||
set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.h"]]
|
||||
set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.vh"]]
|
||||
19
fpga/e300artydevkit/script/ip.tcl
Normal file
19
fpga/e300artydevkit/script/ip.tcl
Normal file
@ -0,0 +1,19 @@
|
||||
create_ip -vendor xilinx.com -library ip -name clk_wiz -module_name mmcm -dir $ipdir -force
|
||||
set_property -dict [list \
|
||||
CONFIG.PRIMITIVE {MMCM} \
|
||||
CONFIG.RESET_TYPE {ACTIVE_LOW} \
|
||||
CONFIG.CLKOUT1_USED {true} \
|
||||
CONFIG.CLKOUT2_USED {true} \
|
||||
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {8.388} \
|
||||
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {65.000} \
|
||||
] [get_ips mmcm]
|
||||
|
||||
create_ip -vendor xilinx.com -library ip -name proc_sys_reset -module_name reset_sys -dir $ipdir -force
|
||||
set_property -dict [list \
|
||||
CONFIG.C_EXT_RESET_HIGH {false} \
|
||||
CONFIG.C_AUX_RESET_HIGH {false} \
|
||||
CONFIG.C_NUM_BUS_RST {1} \
|
||||
CONFIG.C_NUM_PERP_RST {1} \
|
||||
CONFIG.C_NUM_INTERCONNECT_ARESETN {1} \
|
||||
CONFIG.C_NUM_PERP_ARESETN {1} \
|
||||
] [get_ips reset_sys]
|
||||
74
fpga/e300artydevkit/script/prologue.tcl
Normal file
74
fpga/e300artydevkit/script/prologue.tcl
Normal file
@ -0,0 +1,74 @@
|
||||
set scriptdir [file dirname [info script]]
|
||||
set commondir [file dirname $scriptdir]
|
||||
set srcdir [file join $commondir src]
|
||||
set constrsdir [file join $commondir constrs]
|
||||
|
||||
set wrkdir [file join [pwd] obj]
|
||||
set ipdir [file join $wrkdir ip]
|
||||
|
||||
set top {system}
|
||||
|
||||
create_project -part $part_fpga -in_memory
|
||||
set_property -dict [list \
|
||||
BOARD_PART $part_board \
|
||||
TARGET_LANGUAGE {Verilog} \
|
||||
SIMULATOR_LANGUAGE {Mixed} \
|
||||
TARGET_SIMULATOR {XSim} \
|
||||
DEFAULT_LIB {xil_defaultlib} \
|
||||
IP_REPO_PATHS $ipdir \
|
||||
] [current_project]
|
||||
|
||||
proc recglob { basedir pattern } {
|
||||
set dirlist [glob -nocomplain -directory $basedir -type d *]
|
||||
set findlist [glob -nocomplain -directory $basedir $pattern]
|
||||
foreach dir $dirlist {
|
||||
set reclist [recglob $dir $pattern]
|
||||
set findlist [concat $findlist $reclist]
|
||||
}
|
||||
return $findlist
|
||||
}
|
||||
|
||||
|
||||
if {[get_filesets -quiet sources_1] eq ""} {
|
||||
create_fileset -srcset sources_1
|
||||
}
|
||||
set obj [current_fileset]
|
||||
|
||||
set srcmainverilogfiles [recglob $srcdir "*.v"]
|
||||
add_files -norecurse -fileset $obj $srcmainverilogfiles
|
||||
|
||||
if {[info exists ::env(EXTRA_VSRCS)]} {
|
||||
set extra_vsrcs [split $::env(EXTRA_VSRCS)]
|
||||
foreach extra_vsrc $extra_vsrcs {
|
||||
add_files -norecurse -fileset $obj $extra_vsrc
|
||||
}
|
||||
}
|
||||
## TODO: These paths and files should come from the caller, not within this script.
|
||||
#if {[file exists [file join $srcdir include verilog]]} {
|
||||
# add_files -norecurse -fileset $obj [file join $srcdir include verilog DebugTransportModuleJtag.v]
|
||||
# add_files -norecurse -fileset $obj [file join $srcdir include verilog AsyncResetReg.v]
|
||||
#}
|
||||
|
||||
set vsrc_top $::env(VSRC_TOP)
|
||||
set vsrc_consts $::env(VSRC_CONSTS)
|
||||
|
||||
set_property verilog_define [list \
|
||||
"VSRC_CONSTS=${vsrc_consts}" \
|
||||
"VSRC_TOP=${vsrc_top}" \
|
||||
] $obj
|
||||
|
||||
add_files -norecurse -fileset $obj $vsrc_top
|
||||
add_files -norecurse -fileset $obj $vsrc_consts
|
||||
|
||||
if {[get_filesets -quiet sim_1] eq ""} {
|
||||
create_fileset -simset sim_1
|
||||
}
|
||||
set obj [current_fileset -simset]
|
||||
add_files -norecurse -fileset $obj [glob -directory $srcdir {*.v}]
|
||||
set_property TOP {tb} $obj
|
||||
|
||||
if {[get_filesets -quiet constrs_1] eq ""} {
|
||||
create_fileset -constrset constrs_1
|
||||
}
|
||||
set obj [current_fileset -constrset]
|
||||
add_files -norecurse -fileset $obj [glob -directory $constrsdir {*.xdc}]
|
||||
1496
fpga/e300artydevkit/src/system.v
Normal file
1496
fpga/e300artydevkit/src/system.v
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user