From 22ee433699dca058f96858c15e7a2b0c33547d63 Mon Sep 17 00:00:00 2001
From: Shreesha Srinath <shreesha@csl.cornell.edu>
Date: Sun, 20 Aug 2017 01:39:45 -0700
Subject: [PATCH] README: Updates to build bootloaders

---
 README.md | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/README.md b/README.md
index fa3f0ac..2498750 100644
--- a/README.md
+++ b/README.md
@@ -13,15 +13,24 @@ Both systems boot autonomously and can be controlled via an external debugger.
 Please read the section corresponding to the kit you are interested in for
 instructions on how to use this repo.
 
+Software Requirement
+--------------------
 
-Freedom E310 Arty FPGA Dev Kit
+To compile the bootloaders for both Freedom E300 Arty and U500 VC707
+FPGA dev kits, the RISC-V software toolchain must be installed locally and
+set the $(RISCV) environment variable to point to the location of where the
+RISC-V toolchains are installed. You can build the toolchain from scratch
+or download the tools here: https://www.sifive.com/products/tools/
+
+
+Freedom E300 Arty FPGA Dev Kit
 ------------------------------
 
-The Freedom E310 Arty FPGA Dev Kit implements a Freedom E310 chip.
+The Freedom E300 Arty FPGA Dev Kit implements a Freedom E300 chip.
 
 ### How to build
 
-The Makefile corresponding to the Freedom E310 Arty FPGA Dev Kit is
+The Makefile corresponding to the Freedom E300 Arty FPGA Dev Kit is
 `Makefile.e300artydevkit` and it consists of two main targets:
 
 - `verilog`: to compile the Chisel source files and generate the Verilog files.