diff --git a/.gitmodules b/.gitmodules
index ac935dd..74f8330 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -6,4 +6,4 @@
 	url = https://github.com/sifive/sifive-blocks.git
 [submodule "fpga-shells"]
 	path = fpga-shells
-	url = https://github.com/sifive/fpga-shells
+	url = https://git.tiband.de/riscv/fpga-shells.git
diff --git a/fpga-shells b/fpga-shells
index 9d02f53..e9625bf 160000
--- a/fpga-shells
+++ b/fpga-shells
@@ -1 +1 @@
-Subproject commit 9d02f530fc53e68fa952466d697509be70247fa2
+Subproject commit e9625bf8ee21c467a8bb6df3f9304c17411c93b6
diff --git a/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala b/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala
index 0fddbf6..46c75bb 100644
--- a/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala
+++ b/src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala
@@ -10,8 +10,7 @@ import freechips.rocketchip.diplomacy._
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.pinctrl.{BasePin}
 
-import sifive.fpgashells.shell.xilinx.vc707shell._
-import sifive.fpgashells.ip.xilinx.{IOBUF}
+import sifive.fpgashells.shell.xilinx.ml507shell._
 
 //-------------------------------------------------------------------------
 // PinGen
@@ -28,7 +27,7 @@ object PinGen {
 //-------------------------------------------------------------------------
 
 class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
-    extends VC707Shell
+    extends ML507Shell
     with HasDebugJTAG {
 
   //-----------------------------------------------------------------------