100 lines
3.7 KiB
C
100 lines
3.7 KiB
C
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// See LICENSE for license details.
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#ifndef _SIFIVE_PLATFORM_H
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#define _SIFIVE_PLATFORM_H
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#include "const.h"
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#include "riscv_test_defaults.h"
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#include "devices/clint.h"
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#include "devices/gpio.h"
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#include "devices/plic.h"
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#include "devices/spi.h"
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#include "devices/uart.h"
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// Some things missing from the official encoding.h
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#if __riscv_xlen == 32
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#define MCAUSE_INT 0x80000000UL
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#define MCAUSE_CAUSE 0x7FFFFFFFUL
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#else
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#define MCAUSE_INT 0x8000000000000000UL
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#define MCAUSE_CAUSE 0x7FFFFFFFFFFFFFFFUL
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#endif
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/****************************************************************************
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* Platform definitions
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*****************************************************************************/
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// CPU info
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#define NUM_CORES 1
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#define GLOBAL_INT_SIZE 15
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#define GLOBAL_INT_MAX_PRIORITY 7
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// Memory map
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#define AXI_PCIE_HOST_1_00_A_CTRL_ADDR _AC(0x50000000,UL)
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#define AXI_PCIE_HOST_1_00_A_CTRL_SIZE _AC(0x4000000,UL)
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#define CLINT_CTRL_ADDR _AC(0x2000000,UL)
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#define CLINT_CTRL_SIZE _AC(0x10000,UL)
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#define DEBUG_CTRL_ADDR _AC(0x0,UL)
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#define DEBUG_CTRL_SIZE _AC(0x1000,UL)
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#define ERROR_MEM_ADDR _AC(0x3000,UL)
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#define ERROR_MEM_SIZE _AC(0x1000,UL)
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#define GPIO_CTRL_ADDR _AC(0x54002000,UL)
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#define GPIO_CTRL_SIZE _AC(0x1000,UL)
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#define MASKROM_MEM_ADDR _AC(0x10000,UL)
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#define MASKROM_MEM_SIZE _AC(0x2000,UL)
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#define MEMORY_MEM_ADDR _AC(0x80000000,UL)
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#define MEMORY_MEM_SIZE _AC(0x40000000,UL)
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#define PLIC_CTRL_ADDR _AC(0xc000000,UL)
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#define PLIC_CTRL_SIZE _AC(0x4000000,UL)
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#define SPI_CTRL_ADDR _AC(0x54001000,UL)
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#define SPI_CTRL_SIZE _AC(0x1000,UL)
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#define TEST_CTRL_ADDR _AC(0x4000,UL)
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#define TEST_CTRL_SIZE _AC(0x1000,UL)
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#define UART_CTRL_ADDR _AC(0x54000000,UL)
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#define UART_CTRL_SIZE _AC(0x1000,UL)
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// IOF masks
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// Interrupt numbers
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#define UART_INT_BASE 1
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#define SPI_INT_BASE 2
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#define GPIO_INT_BASE 3
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#define AXI_PCIE_HOST_1_00_A_INT_BASE 7
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// Helper functions
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#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i)))
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#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
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#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i)))
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// Bulk set bits in `reg` to either 0 or 1.
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// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7
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// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7
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#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); }
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#define AXI_PCIE_HOST_1_00_A_REG(offset) _REG32(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset)
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#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
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#define DEBUG_REG(offset) _REG32(DEBUG_CTRL_ADDR, offset)
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#define ERROR_REG(offset) _REG32(ERROR_CTRL_ADDR, offset)
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#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
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#define MASKROM_REG(offset) _REG32(MASKROM_CTRL_ADDR, offset)
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#define MEMORY_REG(offset) _REG32(MEMORY_CTRL_ADDR, offset)
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#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
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#define SPI_REG(offset) _REG32(SPI_CTRL_ADDR, offset)
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#define TEST_REG(offset) _REG32(TEST_CTRL_ADDR, offset)
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#define UART_REG(offset) _REG32(UART_CTRL_ADDR, offset)
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#define AXI_PCIE_HOST_1_00_A_REG64(offset) _REG64(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset)
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#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset)
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#define DEBUG_REG64(offset) _REG64(DEBUG_CTRL_ADDR, offset)
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#define ERROR_REG64(offset) _REG64(ERROR_CTRL_ADDR, offset)
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#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset)
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#define MASKROM_REG64(offset) _REG64(MASKROM_CTRL_ADDR, offset)
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#define MEMORY_REG64(offset) _REG64(MEMORY_CTRL_ADDR, offset)
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#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset)
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#define SPI_REG64(offset) _REG64(SPI_CTRL_ADDR, offset)
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#define TEST_REG64(offset) _REG64(TEST_CTRL_ADDR, offset)
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#define UART_REG64(offset) _REG64(UART_CTRL_ADDR, offset)
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// Misc
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#endif /* _SIFIVE_PLATFORM_H */
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