2016-11-29 14:23:11 +01:00
|
|
|
# See LICENSE for license details.
|
|
|
|
|
base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
|
|
|
|
|
BUILD_DIR := $(base_dir)/builds/e300artydevkit
|
2017-08-19 03:21:04 +02:00
|
|
|
FPGA_DIR := $(base_dir)/fpga-shells/xilinx
|
|
|
|
|
MODEL := E300ArtyDevKitFPGAChip
|
2016-11-29 14:23:11 +01:00
|
|
|
PROJECT := sifive.freedom.everywhere.e300artydevkit
|
2018-02-25 19:33:25 +01:00
|
|
|
export CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit
|
2017-08-19 03:21:04 +02:00
|
|
|
export CONFIG := E300ArtyDevKitConfig
|
|
|
|
|
export BOARD := arty
|
|
|
|
|
export BOOTROM_DIR := $(base_dir)/bootrom/xip
|
2016-11-29 14:23:11 +01:00
|
|
|
|
|
|
|
|
rocketchip_dir := $(base_dir)/rocket-chip
|
|
|
|
|
sifiveblocks_dir := $(base_dir)/sifive-blocks
|
2017-08-19 03:21:04 +02:00
|
|
|
VSRCS := \
|
2016-11-29 14:23:11 +01:00
|
|
|
$(rocketchip_dir)/vsrc/AsyncResetReg.v \
|
2017-08-19 03:21:04 +02:00
|
|
|
$(rocketchip_dir)/vsrc/plusarg_reader.v \
|
|
|
|
|
$(sifiveblocks_dir)/vsrc/SRLatch.v \
|
|
|
|
|
$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
|
|
|
|
|
$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
|
|
|
|
|
$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
|
2016-11-29 14:23:11 +01:00
|
|
|
|
|
|
|
|
include common.mk
|
