98 lines
4.3 KiB
Tcl
98 lines
4.3 KiB
Tcl
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#MIG
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create_ip -vendor xilinx.com -library ip -name mig_7series -module_name vc707mig -dir $ipdir -force
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set migprj [file join [pwd] $scriptdir {mig.prj}]
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set_property CONFIG.XML_INPUT_FILE $migprj [get_ips vc707mig]
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puts "SCRIPTDIR $scriptdir"
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#AXI_PCIE
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create_ip -vendor xilinx.com -library ip -version 2.8 -name axi_pcie -module_name vc707axi_to_pcie_x1 -dir $ipdir -force
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set_property -dict [list \
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CONFIG.AXIBAR2PCIEBAR_0 {0x60000000} \
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CONFIG.AXIBAR2PCIEBAR_1 {0x00000000} \
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CONFIG.AXIBAR2PCIEBAR_2 {0x00000000} \
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CONFIG.AXIBAR2PCIEBAR_3 {0x00000000} \
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CONFIG.AXIBAR2PCIEBAR_4 {0x00000000} \
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CONFIG.AXIBAR2PCIEBAR_5 {0x00000000} \
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CONFIG.AXIBAR_0 {0x60000000} \
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CONFIG.AXIBAR_1 {0xFFFFFFFF} \
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CONFIG.AXIBAR_2 {0xFFFFFFFF} \
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CONFIG.AXIBAR_3 {0xFFFFFFFF} \
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CONFIG.AXIBAR_4 {0xFFFFFFFF} \
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CONFIG.AXIBAR_5 {0xFFFFFFFF} \
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CONFIG.AXIBAR_AS_0 {true} \
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CONFIG.AXIBAR_AS_1 {false} \
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CONFIG.AXIBAR_AS_2 {false} \
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CONFIG.AXIBAR_AS_3 {false} \
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CONFIG.AXIBAR_AS_4 {false} \
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CONFIG.AXIBAR_AS_5 {false} \
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CONFIG.AXIBAR_HIGHADDR_0 {0x7FFFFFFF} \
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CONFIG.AXIBAR_HIGHADDR_1 {0x00000000} \
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CONFIG.AXIBAR_HIGHADDR_2 {0x00000000} \
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CONFIG.AXIBAR_HIGHADDR_3 {0x00000000} \
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CONFIG.AXIBAR_HIGHADDR_4 {0x00000000} \
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CONFIG.AXIBAR_HIGHADDR_5 {0x00000000} \
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CONFIG.AXIBAR_NUM {1} \
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CONFIG.BAR0_ENABLED {true} \
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CONFIG.BAR0_SCALE {Gigabytes} \
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CONFIG.BAR0_SIZE {4} \
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CONFIG.BAR0_TYPE {Memory} \
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CONFIG.BAR1_ENABLED {false} \
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CONFIG.BAR1_SCALE {N/A} \
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CONFIG.BAR1_SIZE {8} \
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CONFIG.BAR1_TYPE {N/A} \
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CONFIG.BAR2_ENABLED {false} \
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CONFIG.BAR2_SCALE {N/A} \
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CONFIG.BAR2_SIZE {8} \
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CONFIG.BAR2_TYPE {N/A} \
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CONFIG.BAR_64BIT {true} \
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CONFIG.BASEADDR {0x50000000} \
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CONFIG.BASE_CLASS_MENU {Bridge_device} \
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CONFIG.CLASS_CODE {0x060400} \
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CONFIG.COMP_TIMEOUT {50us} \
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CONFIG.Component_Name {design_1_axi_pcie_1_0} \
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CONFIG.DEVICE_ID {0x7111} \
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CONFIG.ENABLE_CLASS_CODE {true} \
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CONFIG.HIGHADDR {0x53FFFFFF} \
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CONFIG.INCLUDE_BAROFFSET_REG {true} \
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CONFIG.INCLUDE_RC {Root_Port_of_PCI_Express_Root_Complex} \
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CONFIG.INTERRUPT_PIN {false} \
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CONFIG.MAX_LINK_SPEED {2.5_GT/s} \
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CONFIG.MSI_DECODE_ENABLED {true} \
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CONFIG.M_AXI_ADDR_WIDTH {32} \
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CONFIG.M_AXI_DATA_WIDTH {64} \
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CONFIG.NO_OF_LANES {X1} \
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CONFIG.NUM_MSI_REQ {0} \
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CONFIG.PCIEBAR2AXIBAR_0_SEC {1} \
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CONFIG.PCIEBAR2AXIBAR_0 {0x00000000} \
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CONFIG.PCIEBAR2AXIBAR_1 {0xFFFFFFFF} \
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CONFIG.PCIEBAR2AXIBAR_1_SEC {1} \
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CONFIG.PCIEBAR2AXIBAR_2 {0xFFFFFFFF} \
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CONFIG.PCIEBAR2AXIBAR_2_SEC {1} \
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CONFIG.PCIE_BLK_LOCN {X1Y1} \
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CONFIG.PCIE_USE_MODE {GES_and_Production} \
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CONFIG.REF_CLK_FREQ {100_MHz} \
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CONFIG.REV_ID {0x00} \
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CONFIG.SLOT_CLOCK_CONFIG {true} \
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CONFIG.SUBSYSTEM_ID {0x0007} \
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CONFIG.SUBSYSTEM_VENDOR_ID {0x10EE} \
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CONFIG.SUB_CLASS_INTERFACE_MENU {Host_bridge} \
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CONFIG.S_AXI_ADDR_WIDTH {32} \
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CONFIG.S_AXI_DATA_WIDTH {64} \
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CONFIG.S_AXI_ID_WIDTH {4} \
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CONFIG.S_AXI_SUPPORTS_NARROW_BURST {false} \
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CONFIG.VENDOR_ID {0x10EE} \
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CONFIG.XLNX_REF_BOARD {None} \
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CONFIG.axi_aclk_loopback {false} \
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CONFIG.en_ext_ch_gt_drp {false} \
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CONFIG.en_ext_clk {false} \
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CONFIG.en_ext_gt_common {false} \
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CONFIG.en_ext_pipe_interface {false} \
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CONFIG.en_transceiver_status_ports {false} \
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CONFIG.no_slv_err {false} \
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CONFIG.rp_bar_hide {true} \
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CONFIG.shared_logic_in_core {false} ] [get_ips vc707axi_to_pcie_x1]
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