80 lines
2.1 KiB
C
80 lines
2.1 KiB
C
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// See LICENSE for license details.
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#ifndef _SIFIVE_SPI_H
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#define _SIFIVE_SPI_H
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/* Register offsets */
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#define SPI_REG_SCKDIV 0x00
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#define SPI_REG_SCKMODE 0x04
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#define SPI_REG_CSID 0x10
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#define SPI_REG_CSDEF 0x14
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#define SPI_REG_CSMODE 0x18
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#define SPI_REG_DCSSCK 0x28
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#define SPI_REG_DSCKCS 0x2a
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#define SPI_REG_DINTERCS 0x2c
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#define SPI_REG_DINTERXFR 0x2e
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#define SPI_REG_FMT 0x40
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#define SPI_REG_TXFIFO 0x48
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#define SPI_REG_RXFIFO 0x4c
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#define SPI_REG_TXCTRL 0x50
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#define SPI_REG_RXCTRL 0x54
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#define SPI_REG_FCTRL 0x60
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#define SPI_REG_FFMT 0x64
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#define SPI_REG_IE 0x70
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#define SPI_REG_IP 0x74
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/* Fields */
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#define SPI_SCK_POL 0x1
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#define SPI_SCK_PHA 0x2
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#define SPI_FMT_PROTO(x) ((x) & 0x3)
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#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
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#define SPI_FMT_DIR(x) (((x) & 0x1) << 3)
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#define SPI_FMT_LEN(x) (((x) & 0xf) << 16)
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/* TXCTRL register */
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#define SPI_TXWM(x) ((x) & 0xffff)
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/* RXCTRL register */
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#define SPI_RXWM(x) ((x) & 0xffff)
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#define SPI_IP_TXWM 0x1
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#define SPI_IP_RXWM 0x2
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#define SPI_FCTRL_EN 0x1
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#define SPI_INSN_CMD_EN 0x1
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#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)
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#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)
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#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)
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#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)
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#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)
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#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)
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#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
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#define SPI_TXFIFO_FULL (1 << 31)
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#define SPI_RXFIFO_EMPTY (1 << 31)
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/* Values */
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#define SPI_CSMODE_AUTO 0
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#define SPI_CSMODE_HOLD 2
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#define SPI_CSMODE_OFF 3
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#define SPI_DIR_RX 0
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#define SPI_DIR_TX 1
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#define SPI_PROTO_S 0
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#define SPI_PROTO_D 1
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#define SPI_PROTO_Q 2
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#define SPI_ENDIAN_MSB 0
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#define SPI_ENDIAN_LSB 1
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#endif /* _SIFIVE_SPI_H */
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