2016-11-29 14:23:11 +01:00
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# See LICENSE for license details.
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base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
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BUILD_DIR := $(base_dir)/builds/u500vc707devkit
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2017-08-19 03:21:04 +02:00
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FPGA_DIR := $(base_dir)/fpga-shells/xilinx
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MODEL := U500VC707DevKitFPGAChip
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2016-11-29 14:23:11 +01:00
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PROJECT := sifive.freedom.unleashed.u500vc707devkit
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2018-02-25 19:33:25 +01:00
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export CONFIG_PROJECT := sifive.freedom.unleashed.u500vc707devkit
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2017-08-19 03:21:04 +02:00
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export CONFIG := U500VC707DevKitConfig
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export BOARD := vc707
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export BOOTROM_DIR := $(base_dir)/bootrom/sdboot
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2016-11-29 14:23:11 +01:00
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rocketchip_dir := $(base_dir)/rocket-chip
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sifiveblocks_dir := $(base_dir)/sifive-blocks
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2017-08-19 03:21:04 +02:00
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VSRCS := \
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2016-11-29 14:23:11 +01:00
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$(rocketchip_dir)/vsrc/AsyncResetReg.v \
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2017-08-19 03:21:04 +02:00
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$(rocketchip_dir)/vsrc/plusarg_reader.v \
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2016-11-29 14:23:11 +01:00
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$(sifiveblocks_dir)/vsrc/SRLatch.v \
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2017-08-19 03:21:04 +02:00
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$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
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$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
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$(FPGA_DIR)/$(BOARD)/vsrc/vc707reset.v \
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$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
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$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
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2016-11-29 14:23:11 +01:00
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include common.mk
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