diff --git a/xilinx/vc707/constraints/vc707-master.xdc b/xilinx/vc707/constraints/vc707-master.xdc
index 778e4f3..cf410e6 100644
--- a/xilinx/vc707/constraints/vc707-master.xdc
+++ b/xilinx/vc707/constraints/vc707-master.xdc
@@ -35,16 +35,16 @@ set_property IOB TRUE [get_cells "uart_rxd_sync/sync_1"]
 
 # PCI Express
 #FMC 1 refclk
-set_property PACKAGE_PIN A10 [get_ports {pci_exp_refclk_rxp}]
-set_property PACKAGE_PIN A9 [get_ports {pci_exp_refclk_rxn}]
-create_clock -name pcie_ref_clk -period 10 [get_ports pci_exp_refclk_rxp]
-set_input_jitter [get_clocks -of_objects [get_ports pci_exp_refclk_rxp]] 0.5
+set_property PACKAGE_PIN A10 [get_ports {pcie_REFCLK_rxp}]
+set_property PACKAGE_PIN A9 [get_ports {pcie_REFCLK_rxn}]
+create_clock -name pcie_ref_clk -period 10 [get_ports pcie_REFCLK_rxp]
+set_input_jitter [get_clocks -of_objects [get_ports pcie_REFCLK_rxp]] 0.5
 
-set_property PACKAGE_PIN H4 [get_ports {pci_exp_txp}]
-set_property PACKAGE_PIN H3 [get_ports {pci_exp_txn}]
+set_property PACKAGE_PIN H4 [get_ports {pcie_pci_exp_txp}]
+set_property PACKAGE_PIN H3 [get_ports {pcie_pci_exp_txn}]
 
-set_property PACKAGE_PIN G6 [get_ports {pci_exp_rxp}]
-set_property PACKAGE_PIN G5 [get_ports {pci_exp_rxn}]
+set_property PACKAGE_PIN G6 [get_ports {pcie_pci_exp_rxp}]
+set_property PACKAGE_PIN G5 [get_ports {pcie_pci_exp_rxn}]
 
 # JTAG
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]