diff --git a/src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala b/src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala
index 1943fd1..404cde8 100644
--- a/src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala
+++ b/src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala
@@ -47,7 +47,7 @@ class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extend
 
     val address_range = AddressRange.fromSets(c.address).head
     require(log2Ceil(address_range.size) == 28, "Max 256MiB DIMMs supported")
-    val crossing = AsynchronousCrossing(8)
+    val crossing = AsynchronousCrossing(1)
 
     val device = new MemoryDevice
     val node = TLManagerNode(
@@ -101,7 +101,7 @@ class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extend
         // Save the source, size and type of the requests in a queue so we
         // can synthesize the right responses in fifo order. The length also
         // determines the maximum number of in-flight requests.
-        val ack_queue = Module(new Queue(new ResponseQueueIO, 4))
+        val ack_queue = Module(new Queue(new ResponseQueueIO, 2))
 
         // Pass data directly to the controller
         controller.io.request_addr := address
@@ -127,7 +127,7 @@ class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extend
         // avoid losing any responses, this queue *must* be at least as wide
         // as the ack queue, so that we can catch all responses, even if the
         // ack queue is completely filled with read requests.
-        val response_queue = Module(new Queue(controller.io.response_data, 4))
+        val response_queue = Module(new Queue(controller.io.response_data, 2))
 
         response_queue.io.enq.bits  := controller.io.response_data
         response_queue.io.enq.valid := controller.io.response_valid