diff --git a/src/main/scala/shell/xilinx/ML507Shell.scala b/src/main/scala/shell/xilinx/ML507Shell.scala
index cfaca4f..02ed228 100644
--- a/src/main/scala/shell/xilinx/ML507Shell.scala
+++ b/src/main/scala/shell/xilinx/ML507Shell.scala
@@ -13,6 +13,7 @@ import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.chiplink._
+import sifive.blocks.devices.terminal._
 
 import sifive.fpgashells.ip.xilinx.{IBUFDS, PowerOnResetFPGAOnly, sdio_spi_bridge, ml507_sys_clock , vc707reset}
 
@@ -90,6 +91,8 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
   val clock_led            = IO(Output(Clock()))
   val reset_led            = IO(Output(Bool()))
 
+  val dvi                  = IO(new TerminalDVIIO)
+
   //-----------------------------------------------------------------------
   // Wire declrations
   //-----------------------------------------------------------------------
@@ -126,7 +129,7 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
   // Clock Generator
   //-----------------------------------------------------------------------
 
-  //50MHz (37.5MHz)
+  // 48 MHz (TMP, normally 50 MHz)
   val ml507_sys_clock = Module(new ml507_sys_clock)
   ml507_sys_clock.io.CLKIN_IN := sys_clock.asUInt
   val clk50 = ml507_sys_clock.io.CLKFX_OUT
@@ -155,6 +158,16 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
   clock_led := dut_clock
   reset_led := dut_reset
 
+  //-----------------------------------------------------------------------
+  // Terminal
+  //-----------------------------------------------------------------------
+
+  def connectTerminal(dut: HasPeripheryTerminalModuleImp): Unit = {
+    dvi <> dut.dvi
+    dut.terminal.clk := dut_clock
+    dut.terminal.reset := dut_reset
+  }
+
   //-----------------------------------------------------------------------
   // UART
   //-----------------------------------------------------------------------