From 8329b232e23c63267c0ea9f996199af38afc52f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Klemens=20Sch=C3=B6lhorn?= Date: Thu, 19 Apr 2018 01:25:31 +0200 Subject: [PATCH] Hold ml507 in reset while clock not locked --- src/main/scala/ip/xilinx/Xilinx.scala | 1 + src/main/scala/shell/xilinx/ML507Shell.scala | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/main/scala/ip/xilinx/Xilinx.scala b/src/main/scala/ip/xilinx/Xilinx.scala index 779335c..0d6c4ec 100644 --- a/src/main/scala/ip/xilinx/Xilinx.scala +++ b/src/main/scala/ip/xilinx/Xilinx.scala @@ -99,6 +99,7 @@ class ml507_sys_clock extends BlackBox { val io = new Bundle { val CLKIN_IN = Bool(INPUT) val CLKFX_OUT = Clock(OUTPUT) + val LOCKED_OUT = Bool(OUTPUT) } } diff --git a/src/main/scala/shell/xilinx/ML507Shell.scala b/src/main/scala/shell/xilinx/ML507Shell.scala index 9c80301..08079c3 100644 --- a/src/main/scala/shell/xilinx/ML507Shell.scala +++ b/src/main/scala/shell/xilinx/ML507Shell.scala @@ -163,6 +163,7 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule { val pcie_dat_clock = Wire(Clock()) val pcie_cfg_clock = Wire(Clock()) val mmcm_lock_pcie = Wire(Bool()) + val clk_locked = Wire(Bool()) //----------------------------------------------------------------------- @@ -186,6 +187,7 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule { val ml507_sys_clock = Module(new ml507_sys_clock) ml507_sys_clock.io.CLKIN_IN := sys_clock.asUInt val clk50 = ml507_sys_clock.io.CLKFX_OUT + clk_locked := ml507_sys_clock.io.LOCKED_OUT // DUT clock dut_clock := clk50 @@ -194,7 +196,7 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule { // System reset //----------------------------------------------------------------------- - do_reset := !mig_mmcm_locked || !mmcm_lock_pcie || mig_sys_reset + do_reset := !clk_locked || sys_reset mig_resetn := !mig_reset dut_resetn := !dut_reset pcie_dat_resetn := !pcie_dat_reset