diff --git a/build.sbt b/build.sbt deleted file mode 100644 index ebc8ff3..0000000 --- a/build.sbt +++ /dev/null @@ -1,9 +0,0 @@ -// See LICENSE for license details. - -organization := "com.sifive" - -version := "1.0" - -name := "fpga-shells" - -scalaVersion := "2.11.7" diff --git a/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala index 127ed56..1280b3e 100644 --- a/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala +++ b/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala @@ -10,20 +10,30 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import sifive.fpgashells.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig} -trait HasXilinxVC707MIGParameters { +case class XilinxVC707MIGParams( + address : Seq[AddressSet] +) + +class XilinxVC707MIGPads(depth : BigInt) extends VC707MIGIODDR(depth) { + def this(c : XilinxVC707MIGParams) { + this(AddressRange.fromSets(c.address).head.size) + } } -class XilinxVC707MIGPads extends Bundle with VC707MIGIODDR +class XilinxVC707MIGIO(depth : BigInt) extends VC707MIGIODDR(depth) with VC707MIGIOClocksReset -class XilinxVC707MIGIO extends Bundle with VC707MIGIODDR - with VC707MIGIOClocksReset - -class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters { +class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends LazyModule { + val ranges = AddressRange.fromSets(c.address) + require (ranges.size == 1, "DDR range must be contiguous") + val offset = ranges.head.base + val depth = ranges.head.size + require((depth<=0x100000000L),"vc707mig supports upto 4GB depth configuraton") + val device = new MemoryDevice val node = TLInputNode() val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters( - slaves = Seq(AXI4SlaveParameters( - address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)), + slaves = Seq(AXI4SlaveParameters( + address = c.address, resources = device.reg, regionType = RegionType.UNCACHED, executable = true, @@ -48,12 +58,12 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC lazy val module = new LazyModuleImp(this) { val io = new Bundle { - val port = new XilinxVC707MIGIO + val port = new XilinxVC707MIGIO(depth) val tl = node.bundleIn } //MIG black box instantiation - val blackbox = Module(new vc707mig) + val blackbox = Module(new vc707mig(depth)) //pins to top level @@ -102,9 +112,12 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC //app_ref_ack := unconnected //app_zq_ack := unconnected + val awaddr = axi_async.aw.bits.addr - UInt(offset) + val araddr = axi_async.ar.bits.addr - UInt(offset) + //slave AXI interface write address ports blackbox.io.s_axi_awid := axi_async.aw.bits.id - blackbox.io.s_axi_awaddr := axi_async.aw.bits.addr //truncation ?? + blackbox.io.s_axi_awaddr := awaddr //truncated blackbox.io.s_axi_awlen := axi_async.aw.bits.len blackbox.io.s_axi_awsize := axi_async.aw.bits.size blackbox.io.s_axi_awburst := axi_async.aw.bits.burst @@ -130,7 +143,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC //slave AXI interface read address ports blackbox.io.s_axi_arid := axi_async.ar.bits.id - blackbox.io.s_axi_araddr := axi_async.ar.bits.addr //truncation ?? + blackbox.io.s_axi_araddr := araddr // truncated blackbox.io.s_axi_arlen := axi_async.ar.bits.len blackbox.io.s_axi_arsize := axi_async.ar.bits.size blackbox.io.s_axi_arburst := axi_async.ar.bits.burst diff --git a/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIGPeriphery.scala b/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIGPeriphery.scala index 5d80226..667c659 100644 --- a/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIGPeriphery.scala +++ b/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIGPeriphery.scala @@ -2,13 +2,16 @@ package sifive.fpgashells.devices.xilinx.xilinxvc707mig import Chisel._ +import freechips.rocketchip.config._ import freechips.rocketchip.coreplex.HasMemoryBus -import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} +import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp, AddressRange} + +case object MemoryXilinxDDRKey extends Field[XilinxVC707MIGParams] trait HasMemoryXilinxVC707MIG extends HasMemoryBus { val module: HasMemoryXilinxVC707MIGModuleImp - val xilinxvc707mig = LazyModule(new XilinxVC707MIG) + val xilinxvc707mig = LazyModule(new XilinxVC707MIG(p(MemoryXilinxDDRKey))) require(nMemoryChannels == 1, "Coreplex must have 1 master memory port") xilinxvc707mig.node := memBuses.head.toDRAMController @@ -24,7 +27,10 @@ trait HasMemoryXilinxVC707MIGBundle { trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp with HasMemoryXilinxVC707MIGBundle { val outer: HasMemoryXilinxVC707MIG - val xilinxvc707mig = IO(new XilinxVC707MIGIO) + val ranges = AddressRange.fromSets(p(MemoryXilinxDDRKey).address) + require (ranges.size == 1, "DDR range must be contiguous") + val depth = ranges.head.size + val xilinxvc707mig = IO(new XilinxVC707MIGIO(depth)) xilinxvc707mig <> outer.xilinxvc707mig.module.io.port } diff --git a/src/main/scala/ip/xilinx/Xilinx.scala b/src/main/scala/ip/xilinx/Xilinx.scala index d92fe3f..38fac92 100644 --- a/src/main/scala/ip/xilinx/Xilinx.scala +++ b/src/main/scala/ip/xilinx/Xilinx.scala @@ -4,6 +4,7 @@ package sifive.fpgashells.ip.xilinx import Chisel._ import chisel3.core.{Input, Output, attach} import chisel3.experimental.{Analog} +import freechips.rocketchip.util.{ElaborationArtefacts} import sifive.blocks.devices.pinctrl.{BasePin} @@ -204,6 +205,55 @@ class vc707clk_wiz_sync extends BlackBox { val reset = Bool(INPUT) val locked = Bool(OUTPUT) } + + ElaborationArtefacts.add( + "vc707clk_wiz_sync.vivado.tcl", + """create_ip -name clk_wiz -vendor xilinx.com -library ip -version 5.3 -module_name vc707clk_wiz_sync -dir $ipdir -force + set_property -dict [list \ + CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ + CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLKOUT5_USED {true} \ + CONFIG.CLKOUT6_USED {true} \ + CONFIG.CLKOUT7_USED {true} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.5} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {25} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {37.5} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {50} \ + CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {100} \ + CONFIG.CLKOUT6_REQUESTED_OUT_FREQ {150.000} \ + CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {75} \ + CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ + CONFIG.PRIM_IN_FREQ {200.000} \ + CONFIG.CLKIN1_JITTER_PS {50.0} \ + CONFIG.MMCM_DIVCLK_DIVIDE {1} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {4.500} \ + CONFIG.MMCM_CLKIN1_PERIOD {5.0} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {72.000} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {36} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {24} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {18} \ + CONFIG.MMCM_CLKOUT4_DIVIDE {9} \ + CONFIG.MMCM_CLKOUT5_DIVIDE {6} \ + CONFIG.MMCM_CLKOUT6_DIVIDE {12} \ + CONFIG.NUM_OUT_CLKS {7} \ + CONFIG.CLKOUT1_JITTER {168.247} \ + CONFIG.CLKOUT1_PHASE_ERROR {91.235} \ + CONFIG.CLKOUT2_JITTER {146.624} \ + CONFIG.CLKOUT2_PHASE_ERROR {91.235} \ + CONFIG.CLKOUT3_JITTER {135.178} \ + CONFIG.CLKOUT3_PHASE_ERROR {91.235} \ + CONFIG.CLKOUT4_JITTER {127.364} \ + CONFIG.CLKOUT4_PHASE_ERROR {91.235} \ + CONFIG.CLKOUT5_JITTER {110.629} \ + CONFIG.CLKOUT5_PHASE_ERROR {91.235} \ + CONFIG.CLKOUT6_JITTER {102.207} \ + CONFIG.CLKOUT6_PHASE_ERROR {91.235} \ + CONFIG.CLKOUT7_JITTER {117.249} \ + CONFIG.CLKOUT7_PHASE_ERROR {91.235}] [get_ips vc707clk_wiz_sync] """ + ) } //------------------------------------------------------------------------- diff --git a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala index 8f3eece..fe9221b 100644 --- a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala +++ b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala @@ -6,6 +6,7 @@ import freechips.rocketchip.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple} +import freechips.rocketchip.util.{ElaborationArtefacts} // IP VLNV: xilinx.com:customize_ip:vc707pcietoaxi:1.0 // Black Box @@ -398,4 +399,95 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule blackbox.io.m_axi_rvalid := m.r.valid m.r.ready := blackbox.io.m_axi_rready } + + ElaborationArtefacts.add( + "vc707axi_to_pcie_x1.vivado.tcl", + """ + create_ip -vendor xilinx.com -library ip -version 2.8 -name axi_pcie -module_name vc707axi_to_pcie_x1 -dir $ipdir -force + set_property -dict [list \ + CONFIG.AXIBAR2PCIEBAR_0 {0x60000000} \ + CONFIG.AXIBAR2PCIEBAR_1 {0x00000000} \ + CONFIG.AXIBAR2PCIEBAR_2 {0x00000000} \ + CONFIG.AXIBAR2PCIEBAR_3 {0x00000000} \ + CONFIG.AXIBAR2PCIEBAR_4 {0x00000000} \ + CONFIG.AXIBAR2PCIEBAR_5 {0x00000000} \ + CONFIG.AXIBAR_0 {0x60000000} \ + CONFIG.AXIBAR_1 {0xFFFFFFFF} \ + CONFIG.AXIBAR_2 {0xFFFFFFFF} \ + CONFIG.AXIBAR_3 {0xFFFFFFFF} \ + CONFIG.AXIBAR_4 {0xFFFFFFFF} \ + CONFIG.AXIBAR_5 {0xFFFFFFFF} \ + CONFIG.AXIBAR_AS_0 {true} \ + CONFIG.AXIBAR_AS_1 {false} \ + CONFIG.AXIBAR_AS_2 {false} \ + CONFIG.AXIBAR_AS_3 {false} \ + CONFIG.AXIBAR_AS_4 {false} \ + CONFIG.AXIBAR_AS_5 {false} \ + CONFIG.AXIBAR_HIGHADDR_0 {0x7FFFFFFF} \ + CONFIG.AXIBAR_HIGHADDR_1 {0x00000000} \ + CONFIG.AXIBAR_HIGHADDR_2 {0x00000000} \ + CONFIG.AXIBAR_HIGHADDR_3 {0x00000000} \ + CONFIG.AXIBAR_HIGHADDR_4 {0x00000000} \ + CONFIG.AXIBAR_HIGHADDR_5 {0x00000000} \ + CONFIG.AXIBAR_NUM {1} \ + CONFIG.BAR0_ENABLED {true} \ + CONFIG.BAR0_SCALE {Gigabytes} \ + CONFIG.BAR0_SIZE {4} \ + CONFIG.BAR0_TYPE {Memory} \ + CONFIG.BAR1_ENABLED {false} \ + CONFIG.BAR1_SCALE {N/A} \ + CONFIG.BAR1_SIZE {8} \ + CONFIG.BAR1_TYPE {N/A} \ + CONFIG.BAR2_ENABLED {false} \ + CONFIG.BAR2_SCALE {N/A} \ + CONFIG.BAR2_SIZE {8} \ + CONFIG.BAR2_TYPE {N/A} \ + CONFIG.BAR_64BIT {true} \ + CONFIG.BASEADDR {0x50000000} \ + CONFIG.BASE_CLASS_MENU {Bridge_device} \ + CONFIG.CLASS_CODE {0x060400} \ + CONFIG.COMP_TIMEOUT {50ms} \ + CONFIG.Component_Name {design_1_axi_pcie_1_0} \ + CONFIG.DEVICE_ID {0x7111} \ + CONFIG.ENABLE_CLASS_CODE {true} \ + CONFIG.HIGHADDR {0x53FFFFFF} \ + CONFIG.INCLUDE_BAROFFSET_REG {true} \ + CONFIG.INCLUDE_RC {Root_Port_of_PCI_Express_Root_Complex} \ + CONFIG.INTERRUPT_PIN {false} \ + CONFIG.MAX_LINK_SPEED {2.5_GT/s} \ + CONFIG.MSI_DECODE_ENABLED {true} \ + CONFIG.M_AXI_ADDR_WIDTH {32} \ + CONFIG.M_AXI_DATA_WIDTH {64} \ + CONFIG.NO_OF_LANES {X1} \ + CONFIG.NUM_MSI_REQ {0} \ + CONFIG.PCIEBAR2AXIBAR_0_SEC {1} \ + CONFIG.PCIEBAR2AXIBAR_0 {0x00000000} \ + CONFIG.PCIEBAR2AXIBAR_1 {0xFFFFFFFF} \ + CONFIG.PCIEBAR2AXIBAR_1_SEC {1} \ + CONFIG.PCIEBAR2AXIBAR_2 {0xFFFFFFFF} \ + CONFIG.PCIEBAR2AXIBAR_2_SEC {1} \ + CONFIG.PCIE_BLK_LOCN {X1Y1} \ + CONFIG.PCIE_USE_MODE {GES_and_Production} \ + CONFIG.REF_CLK_FREQ {100_MHz} \ + CONFIG.REV_ID {0x00} \ + CONFIG.SLOT_CLOCK_CONFIG {true} \ + CONFIG.SUBSYSTEM_ID {0x0007} \ + CONFIG.SUBSYSTEM_VENDOR_ID {0x10EE} \ + CONFIG.SUB_CLASS_INTERFACE_MENU {Host_bridge} \ + CONFIG.S_AXI_ADDR_WIDTH {32} \ + CONFIG.S_AXI_DATA_WIDTH {64} \ + CONFIG.S_AXI_ID_WIDTH {4} \ + CONFIG.S_AXI_SUPPORTS_NARROW_BURST {false} \ + CONFIG.VENDOR_ID {0x10EE} \ + CONFIG.XLNX_REF_BOARD {None} \ + CONFIG.axi_aclk_loopback {false} \ + CONFIG.en_ext_ch_gt_drp {false} \ + CONFIG.en_ext_clk {false} \ + CONFIG.en_ext_gt_common {false} \ + CONFIG.en_ext_pipe_interface {false} \ + CONFIG.en_transceiver_status_ports {false} \ + CONFIG.no_slv_err {false} \ + CONFIG.rp_bar_hide {true} \ + CONFIG.shared_logic_in_core {false} ] [get_ips vc707axi_to_pcie_x1]""" + ) } diff --git a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala index d06b68c..d5d58ab 100644 --- a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala +++ b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala @@ -3,13 +3,16 @@ package sifive.fpgashells.ip.xilinx.vc707mig import Chisel._ import chisel3.experimental.{Analog,attach} +import freechips.rocketchip.util.{ElaborationArtefacts} +import freechips.rocketchip.util.GenericParameterizedBundle import freechips.rocketchip.config._ // IP VLNV: xilinx.com:customize_ip:vc707mig:1.0 // Black Box -trait VC707MIGIODDR extends Bundle { - val ddr3_addr = Bits(OUTPUT,14) +class VC707MIGIODDR(depth : BigInt) extends GenericParameterizedBundle(depth) { + require((depth<=0x100000000L),"VC707MIGIODDR supports upto 4GB depth configuraton") + val ddr3_addr = Bits(OUTPUT,if(depth<=0x40000000L) 14 else 16) val ddr3_ba = Bits(OUTPUT,3) val ddr3_ras_n = Bool(OUTPUT) val ddr3_cas_n = Bool(OUTPUT) @@ -44,10 +47,12 @@ trait VC707MIGIOClocksReset extends Bundle { //scalastyle:off //turn off linter: blackbox name must match verilog module -class vc707mig(implicit val p:Parameters) extends BlackBox +class vc707mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox { - val io = new Bundle with VC707MIGIODDR - with VC707MIGIOClocksReset { + require((depth<=0x100000000L),"vc707mig supports upto 4GB depth configuraton") + override def desiredName = if(depth<=0x40000000) "vc707mig1gb" else "vc707mig4gb" + + val io = new VC707MIGIODDR(depth) with VC707MIGIOClocksReset { // User interface signals val app_sr_req = Bool(INPUT) val app_ref_req = Bool(INPUT) @@ -58,7 +63,7 @@ class vc707mig(implicit val p:Parameters) extends BlackBox //axi_s //slave interface write address ports val s_axi_awid = Bits(INPUT,4) - val s_axi_awaddr = Bits(INPUT,30) + val s_axi_awaddr = Bits(INPUT,if(depth<=0x40000000) 30 else 32) val s_axi_awlen = Bits(INPUT,8) val s_axi_awsize = Bits(INPUT,3) val s_axi_awburst = Bits(INPUT,2) @@ -81,7 +86,7 @@ class vc707mig(implicit val p:Parameters) extends BlackBox val s_axi_bvalid = Bool(OUTPUT) //slave interface read address ports val s_axi_arid = Bits(INPUT,4) - val s_axi_araddr = Bits(INPUT,30) + val s_axi_araddr = Bits(INPUT,if(depth<=0x40000000) 30 else 32) val s_axi_arlen = Bits(INPUT,8) val s_axi_arsize = Bits(INPUT,3) val s_axi_arburst = Bits(INPUT,2) @@ -101,5 +106,429 @@ class vc707mig(implicit val p:Parameters) extends BlackBox //misc val device_temp = Bits(OUTPUT,12) } + + val vc707mig1gbprj = """ { + + + vc707mig1gp + 1 + 1 + OFF + 1024 + ON + Enabled + xc7vx485t-ffg1761/-2 + 3.0 + No Buffer + Use System Clock + ACTIVE HIGH + FALSE + 0 + 50 Ohms + 0 + + DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6 + 1250 + 2.0V + 4:1 + 200 + 0 + 800 + 1.000 + 1 + 1 + 1 + 1 + 64 + 1 + 1 + Disabled + Normal + FALSE + + 14 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 11 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 8 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 30 + 64 + 4 + 0 + + + + } """ + + val vc707mig4gbprj = """ { + + + vc707mig4gb + 1 + 1 + OFF + 1024 + ON + Enabled + xc7vx485t-ffg1761/-2 + 3.0 + No Buffer + Use System Clock + ACTIVE HIGH + FALSE + 0 + 50 Ohms + 0 + + DDR3_SDRAM/SODIMMs/MT8KTF51264HZ-1G9 + 1250 + 2.0V + 4:1 + 200 + 0 + 800 + 1.000 + 1 + 1 + 1 + 1 + 64 + 1 + 1 + Disabled + Normal + FALSE + + 16 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 11 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 8 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 32 + 64 + 4 + 0 + + + +}""" + + val migprj = if(depth<=0x40000000) vc707mig1gbprj else vc707mig4gbprj + val migprjname = if(depth<=0x40000000) """{/vc707mig1gb.prj}""" else """{/vc707mig4gb.prj}""" + val modulename = if(depth<=0x40000000) """vc707mig1gb""" else """vc707mig4gb""" + + + ElaborationArtefacts.add( + modulename++".vivado.tcl", + """set migprj """++migprj++""" + set migprjfile """++migprjname++""" + set migprjfilepath $ipdir$migprjfile + set fp [open $migprjfilepath w+] + puts $fp $migprj + close $fp + create_ip -vendor xilinx.com -library ip -name mig_7series -module_name """ ++ modulename ++ """ -dir $ipdir -force + set_property CONFIG.XML_INPUT_FILE $migprjfilepath [get_ips """ ++ modulename ++ """] """ + ) + + } //scalastyle:on diff --git a/src/main/scala/shell/xilinx/VC707Shell.scala b/src/main/scala/shell/xilinx/VC707Shell.scala index b3b1a58..e2b7494 100644 --- a/src/main/scala/shell/xilinx/VC707Shell.scala +++ b/src/main/scala/shell/xilinx/VC707Shell.scala @@ -35,7 +35,7 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule { val reset = IO(Input(Bool())) // DDR SDRAM - val ddr3_addr = IO(Output(UInt(14.W))) + val ddr3_addr = IO(Output(UInt(16.W))) val ddr3_ba = IO(Output(UInt(3.W))) val ddr3_cas_n = IO(Output(Bool())) val ddr3_ck_p = IO(Output(Bool())) diff --git a/xilinx/Makefile b/xilinx/Makefile index ec6c75f..1416927 100644 --- a/xilinx/Makefile +++ b/xilinx/Makefile @@ -14,7 +14,7 @@ init = $(FPGA_BUILD_DIR)/.init $(init): $(fpga_common_script_dir)/init.tcl mkdir -p $(FPGA_BUILD_DIR) && \ cd $(FPGA_BUILD_DIR) && \ - VSRCS="$(VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source $< + VSRCS="$(VSRCS)" IPVIVADOTCLS="$(IPVIVADOTCLS)" $(VIVADO) $(VIVADOFLAGS) -source $< .PHONY: init init: $(init) diff --git a/xilinx/common/tcl/init.tcl b/xilinx/common/tcl/init.tcl index 49b8dc5..c555e59 100644 --- a/xilinx/common/tcl/init.tcl +++ b/xilinx/common/tcl/init.tcl @@ -9,8 +9,15 @@ file mkdir $ipdir # Update the IP catalog update_ip_catalog -rebuild -# Board specific IP implementation -source [file join $boarddir tcl ip.tcl] +# Generate IP implementations. Vivado TCL emitted from Chisel Blackboxes +foreach ipvivadotcl $ipvivadotcls { + source $ipvivadotcl +} +# Optional board-specific ip script +set boardiptcl [file join $boarddir tcl ip.tcl] +if {[file exists boardiptcl]} { + source [file join $boarddir tcl ip.tcl] +} # AR 58526 set_property GENERATE_SYNTH_CHECKPOINT {false} [get_files -all {*.xci}] diff --git a/xilinx/common/tcl/prologue.tcl b/xilinx/common/tcl/prologue.tcl index 77615fe..9fee57d 100644 --- a/xilinx/common/tcl/prologue.tcl +++ b/xilinx/common/tcl/prologue.tcl @@ -51,6 +51,13 @@ if {[info exists ::env(VSRCS)]} { } } +# Add IP Vivado TCL from IPVIVADOTCL environment variable +if {[info exists ::env(IPVIVADOTCLS)]} { + # Split string into words even with multiple consecutive spaces + # http://wiki.tcl.tk/989 + set ipvivadotcls [regexp -inline -all -- {\S+} $::env(IPVIVADOTCLS)] +} + if {[get_filesets -quiet sim_1] eq ""} { create_fileset -simset sim_1 } diff --git a/xilinx/vc707/tcl/ip.tcl b/xilinx/vc707/tcl/ip.tcl deleted file mode 100644 index 82def13..0000000 --- a/xilinx/vc707/tcl/ip.tcl +++ /dev/null @@ -1,140 +0,0 @@ -# See LICENSE for license details. -#MIG -create_ip -vendor xilinx.com -library ip -name mig_7series -module_name vc707mig -dir $ipdir -force -set migprj [file join $boarddir tcl {mig.prj}] -set_property CONFIG.XML_INPUT_FILE $migprj [get_ips vc707mig] - -#AXI_PCIE -create_ip -vendor xilinx.com -library ip -version 2.8 -name axi_pcie -module_name vc707axi_to_pcie_x1 -dir $ipdir -force -set_property -dict [list \ -CONFIG.AXIBAR2PCIEBAR_0 {0x60000000} \ -CONFIG.AXIBAR2PCIEBAR_1 {0x00000000} \ -CONFIG.AXIBAR2PCIEBAR_2 {0x00000000} \ -CONFIG.AXIBAR2PCIEBAR_3 {0x00000000} \ -CONFIG.AXIBAR2PCIEBAR_4 {0x00000000} \ -CONFIG.AXIBAR2PCIEBAR_5 {0x00000000} \ -CONFIG.AXIBAR_0 {0x60000000} \ -CONFIG.AXIBAR_1 {0xFFFFFFFF} \ -CONFIG.AXIBAR_2 {0xFFFFFFFF} \ -CONFIG.AXIBAR_3 {0xFFFFFFFF} \ -CONFIG.AXIBAR_4 {0xFFFFFFFF} \ -CONFIG.AXIBAR_5 {0xFFFFFFFF} \ -CONFIG.AXIBAR_AS_0 {true} \ -CONFIG.AXIBAR_AS_1 {false} \ -CONFIG.AXIBAR_AS_2 {false} \ -CONFIG.AXIBAR_AS_3 {false} \ -CONFIG.AXIBAR_AS_4 {false} \ -CONFIG.AXIBAR_AS_5 {false} \ -CONFIG.AXIBAR_HIGHADDR_0 {0x7FFFFFFF} \ -CONFIG.AXIBAR_HIGHADDR_1 {0x00000000} \ -CONFIG.AXIBAR_HIGHADDR_2 {0x00000000} \ -CONFIG.AXIBAR_HIGHADDR_3 {0x00000000} \ -CONFIG.AXIBAR_HIGHADDR_4 {0x00000000} \ -CONFIG.AXIBAR_HIGHADDR_5 {0x00000000} \ -CONFIG.AXIBAR_NUM {1} \ -CONFIG.BAR0_ENABLED {true} \ -CONFIG.BAR0_SCALE {Gigabytes} \ -CONFIG.BAR0_SIZE {4} \ -CONFIG.BAR0_TYPE {Memory} \ -CONFIG.BAR1_ENABLED {false} \ -CONFIG.BAR1_SCALE {N/A} \ -CONFIG.BAR1_SIZE {8} \ -CONFIG.BAR1_TYPE {N/A} \ -CONFIG.BAR2_ENABLED {false} \ -CONFIG.BAR2_SCALE {N/A} \ -CONFIG.BAR2_SIZE {8} \ -CONFIG.BAR2_TYPE {N/A} \ -CONFIG.BAR_64BIT {true} \ -CONFIG.BASEADDR {0x50000000} \ -CONFIG.BASE_CLASS_MENU {Bridge_device} \ -CONFIG.CLASS_CODE {0x060400} \ -CONFIG.COMP_TIMEOUT {50ms} \ -CONFIG.Component_Name {design_1_axi_pcie_1_0} \ -CONFIG.DEVICE_ID {0x7111} \ -CONFIG.ENABLE_CLASS_CODE {true} \ -CONFIG.HIGHADDR {0x53FFFFFF} \ -CONFIG.INCLUDE_BAROFFSET_REG {true} \ -CONFIG.INCLUDE_RC {Root_Port_of_PCI_Express_Root_Complex} \ -CONFIG.INTERRUPT_PIN {false} \ -CONFIG.MAX_LINK_SPEED {2.5_GT/s} \ -CONFIG.MSI_DECODE_ENABLED {true} \ -CONFIG.M_AXI_ADDR_WIDTH {32} \ -CONFIG.M_AXI_DATA_WIDTH {64} \ -CONFIG.NO_OF_LANES {X1} \ -CONFIG.NUM_MSI_REQ {0} \ -CONFIG.PCIEBAR2AXIBAR_0_SEC {1} \ -CONFIG.PCIEBAR2AXIBAR_0 {0x00000000} \ -CONFIG.PCIEBAR2AXIBAR_1 {0xFFFFFFFF} \ -CONFIG.PCIEBAR2AXIBAR_1_SEC {1} \ -CONFIG.PCIEBAR2AXIBAR_2 {0xFFFFFFFF} \ -CONFIG.PCIEBAR2AXIBAR_2_SEC {1} \ -CONFIG.PCIE_BLK_LOCN {X1Y1} \ -CONFIG.PCIE_USE_MODE {GES_and_Production} \ -CONFIG.REF_CLK_FREQ {100_MHz} \ -CONFIG.REV_ID {0x00} \ -CONFIG.SLOT_CLOCK_CONFIG {true} \ -CONFIG.SUBSYSTEM_ID {0x0007} \ -CONFIG.SUBSYSTEM_VENDOR_ID {0x10EE} \ -CONFIG.SUB_CLASS_INTERFACE_MENU {Host_bridge} \ -CONFIG.S_AXI_ADDR_WIDTH {32} \ -CONFIG.S_AXI_DATA_WIDTH {64} \ -CONFIG.S_AXI_ID_WIDTH {4} \ -CONFIG.S_AXI_SUPPORTS_NARROW_BURST {false} \ -CONFIG.VENDOR_ID {0x10EE} \ -CONFIG.XLNX_REF_BOARD {None} \ -CONFIG.axi_aclk_loopback {false} \ -CONFIG.en_ext_ch_gt_drp {false} \ -CONFIG.en_ext_clk {false} \ -CONFIG.en_ext_gt_common {false} \ -CONFIG.en_ext_pipe_interface {false} \ -CONFIG.en_transceiver_status_ports {false} \ -CONFIG.no_slv_err {false} \ -CONFIG.rp_bar_hide {true} \ -CONFIG.shared_logic_in_core {false} ] [get_ips vc707axi_to_pcie_x1] - -#Coreplex clock generator -create_ip -name clk_wiz -vendor xilinx.com -library ip -version 5.3 -module_name vc707clk_wiz_sync -dir $ipdir -force -set_property -dict [list \ - CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ - CONFIG.PRIM_SOURCE {No_buffer} \ - CONFIG.CLKOUT2_USED {true} \ - CONFIG.CLKOUT3_USED {true} \ - CONFIG.CLKOUT4_USED {true} \ - CONFIG.CLKOUT5_USED {true} \ - CONFIG.CLKOUT6_USED {true} \ - CONFIG.CLKOUT7_USED {true} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.5} \ - CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {25} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {37.5} \ - CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {50} \ - CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {100} \ - CONFIG.CLKOUT6_REQUESTED_OUT_FREQ {150.000} \ - CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {75} \ - CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ - CONFIG.PRIM_IN_FREQ {200.000} \ - CONFIG.CLKIN1_JITTER_PS {50.0} \ - CONFIG.MMCM_DIVCLK_DIVIDE {1} \ - CONFIG.MMCM_CLKFBOUT_MULT_F {4.500} \ - CONFIG.MMCM_CLKIN1_PERIOD {5.0} \ - CONFIG.MMCM_CLKOUT0_DIVIDE_F {72.000} \ - CONFIG.MMCM_CLKOUT1_DIVIDE {36} \ - CONFIG.MMCM_CLKOUT2_DIVIDE {24} \ - CONFIG.MMCM_CLKOUT3_DIVIDE {18} \ - CONFIG.MMCM_CLKOUT4_DIVIDE {9} \ - CONFIG.MMCM_CLKOUT5_DIVIDE {6} \ - CONFIG.MMCM_CLKOUT6_DIVIDE {12} \ - CONFIG.NUM_OUT_CLKS {7} \ - CONFIG.CLKOUT1_JITTER {168.247} \ - CONFIG.CLKOUT1_PHASE_ERROR {91.235} \ - CONFIG.CLKOUT2_JITTER {146.624} \ - CONFIG.CLKOUT2_PHASE_ERROR {91.235} \ - CONFIG.CLKOUT3_JITTER {135.178} \ - CONFIG.CLKOUT3_PHASE_ERROR {91.235} \ - CONFIG.CLKOUT4_JITTER {127.364} \ - CONFIG.CLKOUT4_PHASE_ERROR {91.235} \ - CONFIG.CLKOUT5_JITTER {110.629} \ - CONFIG.CLKOUT5_PHASE_ERROR {91.235} \ - CONFIG.CLKOUT6_JITTER {102.207} \ - CONFIG.CLKOUT6_PHASE_ERROR {91.235} \ - CONFIG.CLKOUT7_JITTER {117.249} \ - CONFIG.CLKOUT7_PHASE_ERROR {91.235}] [get_ips vc707clk_wiz_sync] diff --git a/xilinx/vc707/tcl/mig.prj b/xilinx/vc707/tcl/mig.prj deleted file mode 100644 index e105154..0000000 --- a/xilinx/vc707/tcl/mig.prj +++ /dev/null @@ -1,202 +0,0 @@ - - - - vc707mig - 1 - 1 - OFF - 1024 - ON - Enabled - xc7vx485t-ffg1761/-2 - 3.0 - No Buffer - Use System Clock - ACTIVE HIGH - FALSE - 0 - 50 Ohms - 0 - - DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6 - 1250 - 2.0V - 4:1 - 200 - 0 - 800 - 1.000 - 1 - 1 - 1 - 1 - 64 - 1 - 1 - Disabled - Normal - FALSE - - 14 - 10 - 3 - 1.5V - BANK_ROW_COLUMN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8 - Fixed - Sequential - 11 - Normal - No - Slow Exit - Enable - RZQ/7 - Disable - Enable - RZQ/6 - 0 - Disabled - Enabled - Output Buffer Enabled - Full Array - 8 - Enabled - Normal - Dynamic ODT off - AXI - - RD_PRI_REG - 30 - 64 - 4 - 0 - - - -