101 lines
2.8 KiB
C
101 lines
2.8 KiB
C
#define F_CPU 20000000UL
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#include <stdint.h>
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#include <avr/io.h>
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#include <util/delay.h>
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#define BAUD 9600
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#include <util/setbaud.h>
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void uart_init(void) {
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#define BAUDRATE ((F_CPU)/(BAUD*8UL)-1) // set baud rate value for UBRR
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UBRR0H = (BAUDRATE>>8); // shift the register right by 8 bits to get the upper 8 bits
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UBRR0L = BAUDRATE; // set baud rate
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// UCSR0A |= (1 << U2X0); // double transmission speed
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// UCSR0B = (1 << TXEN0) | (1 << RXEN0);
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// UCSR0C = (1 << UCSZ01) | (1 << UCSZ00);
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// UBRR0H = UBRRH_VALUE;
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// UBRR0L = UBRRL_VALUE;
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UCSR0A |= _BV(U2X0);
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// UCSR0A &= ~(_BV(U2X0));
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// UCSR0C = _BV(UCSZ01) | _BV(UCSZ00); /* 8-bit data */
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UCSR0C = 0x06; /* 8-bit data */
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UCSR0B = _BV(RXEN0) | _BV(TXEN0) | _BV(RXCIE0); /* Enable RX and TX */
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}
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/*
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// f=20MHz -> T=0,05 µs
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uint8_t T0H = 6; // == 0.3 µs ~ 0.4 µs (+- 150ns) == [0.25, 0.55] µs
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uint8_t T1H = 14; // == 0.7 µs ~ 0.8 µs (+- 150ns) == [0.65, 0.95] µs
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uint8_t T0L = 15; // == 0.75 µs ~ 0.85µs (+- 150ns) == [0.70, 1.00] µs
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uint8_t T1L = 8; // == 0.35 µs ~ 0.45µs (+- 150ns) == [0.30, 0.60] µs
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uint8_t RES = 51; // > 50 µs
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*/
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#define wait6 __asm__("nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t")
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#define wait8 __asm__("nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t")
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#define wait14 __asm__("nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t")
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#define wait15 __asm__("nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t""nop\n\t")
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uint8_t const CMAX = 32;
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inline void writeZero() {
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PORTC = 1;
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wait6;
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PORTC = 0;
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wait15;
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}
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inline void writeOne() {
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PORTC = 1;
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wait14;
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PORTC = 0;
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wait8;
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}
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int main() {
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DDRC = 1; // PORT C0 output
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// uart_init();
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do{
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// for( int i = 0; i < 7; i++) {
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// if( i%2==0){
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writeZero();writeZero();writeZero();writeZero();writeZero();writeZero();writeZero();writeOne();
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writeZero();writeZero();writeZero();writeZero();writeZero();writeZero();writeZero();writeZero();
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writeZero();writeZero();writeZero();writeZero();writeZero();writeZero();writeZero();writeZero();
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// } else {
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writeZero();writeZero();writeZero();writeZero();writeZero();writeZero();writeZero();writeZero();
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writeZero();writeZero();writeZero();writeZero();writeZero();writeZero();writeZero();writeZero();
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writeZero();writeZero();writeZero();writeZero();writeZero();writeZero();writeZero();writeZero();
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// }
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// }
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_delay_ms(500);
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// loop_until_bit_is_set(UCSR0A, UDRE0);
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// UDR0 = 'D';
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}while(1);
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}
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int main2( void )
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{
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DDRC = 0xff; // (1 << PC0);
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while(1) {
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PORTC ^= 0xff; //(1 << PC0);
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_delay_ms(1000);
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}
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return 0;
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}
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