From da2c20205762574ac2706fb6b035e3f4c421095d Mon Sep 17 00:00:00 2001
From: ht <h.thalheim@gmx.de>
Date: Thu, 22 Mar 2018 15:52:53 +0100
Subject: [PATCH] Added OPV board. Moved Spannungsversorgung.

---
 boards/OPV/OPV-cache.lib                      | 103 ++++
 boards/OPV/OPV.kicad_pcb                      | 543 ++++++++++++++++++
 boards/OPV/OPV.pro                            |  60 ++
 boards/OPV/OPV.sch                            | 289 ++++++++++
 .../Spannungsversorgung-cache.lib             |   0
 .../Spannungsversorgung.kicad_pcb             |   0
 .../Spannungsversorgung.pro                   |   0
 .../Spannungsversorgung.rules                 |   0
 .../Spannungsversorgung.sch                   |   0
 .../components/ceae2594m-5.dcm                |   0
 .../components/ceae2594m-5.lib                |   0
 .../footprints/Inductor18.4x15.kicad_mod      |   0
 .../footprints/USB A.kicad_mod                |   0
 .../footprints/USB-A-SMT-8231.kicad_mod       |   0
 boards/{ => Spannungsversorgung}/fp-lib-table |   0
 documents/OPV-F.Cu.pdf                        | Bin 0 -> 6829 bytes
 16 files changed, 995 insertions(+)
 create mode 100644 boards/OPV/OPV-cache.lib
 create mode 100644 boards/OPV/OPV.kicad_pcb
 create mode 100644 boards/OPV/OPV.pro
 create mode 100644 boards/OPV/OPV.sch
 rename boards/{ => Spannungsversorgung}/Spannungsversorgung-cache.lib (100%)
 rename boards/{ => Spannungsversorgung}/Spannungsversorgung.kicad_pcb (100%)
 rename boards/{ => Spannungsversorgung}/Spannungsversorgung.pro (100%)
 rename boards/{ => Spannungsversorgung}/Spannungsversorgung.rules (100%)
 rename boards/{ => Spannungsversorgung}/Spannungsversorgung.sch (100%)
 rename boards/{ => Spannungsversorgung}/components/ceae2594m-5.dcm (100%)
 rename boards/{ => Spannungsversorgung}/components/ceae2594m-5.lib (100%)
 rename boards/{ => Spannungsversorgung}/footprints/Inductor18.4x15.kicad_mod (100%)
 rename boards/{ => Spannungsversorgung}/footprints/USB A.kicad_mod (100%)
 rename boards/{ => Spannungsversorgung}/footprints/USB-A-SMT-8231.kicad_mod (100%)
 rename boards/{ => Spannungsversorgung}/fp-lib-table (100%)
 create mode 100644 documents/OPV-F.Cu.pdf

diff --git a/boards/OPV/OPV-cache.lib b/boards/OPV/OPV-cache.lib
new file mode 100644
index 0000000..b5c663d
--- /dev/null
+++ b/boards/OPV/OPV-cache.lib
@@ -0,0 +1,103 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CONN_01X07
+#
+DEF CONN_01X07 P 0 40 Y N 1 F N
+F0 "P" 0 400 50 H V C CNN
+F1 "CONN_01X07" 100 0 50 V V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+$FPLIST
+ Pin_Header_Straight_1X07
+ Pin_Header_Angled_1X07
+ Socket_Strip_Straight_1X07
+ Socket_Strip_Angled_1X07
+$ENDFPLIST
+DRAW
+S -50 -350 50 350 0 1 0 N
+S -50 -295 10 -305 0 1 0 N
+S -50 -195 10 -205 0 1 0 N
+S -50 -95 10 -105 0 1 0 N
+S -50 5 10 -5 0 1 0 N
+S -50 105 10 95 0 1 0 N
+S -50 205 10 195 0 1 0 N
+S -50 305 10 295 0 1 0 N
+X P1 1 -200 300 150 R 50 50 1 1 P
+X P2 2 -200 200 150 R 50 50 1 1 P
+X P3 3 -200 100 150 R 50 50 1 1 P
+X P4 4 -200 0 150 R 50 50 1 1 P
+X P5 5 -200 -100 150 R 50 50 1 1 P
+X P6 6 -200 -200 150 R 50 50 1 1 P
+X P7 7 -200 -300 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+P 6 0 1 0  0 0  0 -50  50 -50  0 -100  -50 -50  0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# LM2902N
+#
+DEF LM2902N U 0 20 Y Y 4 F N
+F0 "U" 50 200 50 H V C CNN
+F1 "LM2902N" 150 -200 50 H V C CNN
+F2 "" -50 100 50 H V C CNN
+F3 "" 50 200 50 H V C CNN
+ALIAS LM324 TLC274 TL074 LM324N LM324AN MCP6004
+DRAW
+P 4 0 1 6  -200 200  200 0  -200 -200  -200 200 f
+X V+ 4 -100 300 150 D 50 50 0 1 W
+X V- 11 -100 -300 150 U 50 50 0 1 W
+X ~ 1 300 0 100 L 50 50 1 1 O
+X - 2 -300 -100 100 R 50 50 1 1 I
+X + 3 -300 100 100 R 50 50 1 1 I
+X + 5 -300 100 100 R 50 50 2 1 I
+X - 6 -300 -100 100 R 50 50 2 1 I
+X ~ 7 300 0 100 L 50 50 2 1 O
+X ~ 8 300 0 100 L 50 50 3 1 O
+X - 9 -300 -100 100 R 50 50 3 1 I
+X + 10 -300 100 100 R 50 50 3 1 I
+X + 12 -300 100 100 R 50 50 4 1 I
+X - 13 -300 -100 100 R 50 50 4 1 I
+X ~ 14 300 0 100 L 50 50 4 1 O
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 95 50 H I C CNN
+F1 "PWR_FLAG" 0 180 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0  0 0  0 50  -75 100  0 150  75 100  0 50 N
+ENDDRAW
+ENDDEF
+#
+# VCC
+#
+DEF VCC #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "VCC" 0 150 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+C 0 75 25 0 1 0 N
+P 2 0 1 0  0 0  0 50 N
+X VCC 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/boards/OPV/OPV.kicad_pcb b/boards/OPV/OPV.kicad_pcb
new file mode 100644
index 0000000..418c4e9
--- /dev/null
+++ b/boards/OPV/OPV.kicad_pcb
@@ -0,0 +1,543 @@
+(kicad_pcb (version 4) (host pcbnew 4.0.2+dfsg1-stable)
+
+  (general
+    (links 14)
+    (no_connects 0)
+    (area 134.591667 92.835 162.588334 120.375)
+    (thickness 1.6)
+    (drawings 15)
+    (tracks 30)
+    (zones 0)
+    (modules 3)
+    (nets 15)
+  )
+
+  (page A4)
+  (layers
+    (0 F.Cu signal)
+    (31 B.Cu signal hide)
+    (32 B.Adhes user)
+    (33 F.Adhes user)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.25)
+    (trace_clearance 0.2)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.2)
+    (segment_width 0.2)
+    (edge_width 0.15)
+    (via_size 0.6)
+    (via_drill 0.4)
+    (via_min_size 0.4)
+    (via_min_drill 0.3)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.15)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 2.032 2.032)
+    (pad_drill 1.016)
+    (pad_to_mask_clearance 0.2)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFFFF7F)
+    (pcbplotparams
+      (layerselection 0x00000_00000001)
+      (usegerberextensions false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15)
+      (hpglpenoverlay 2)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 4)
+      (mirror true)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+  (net 1 "Net-(P1-Pad1)")
+  (net 2 "Net-(P1-Pad2)")
+  (net 3 "Net-(P1-Pad3)")
+  (net 4 VCC)
+  (net 5 "Net-(P1-Pad5)")
+  (net 6 "Net-(P1-Pad6)")
+  (net 7 "Net-(P1-Pad7)")
+  (net 8 "Net-(P2-Pad1)")
+  (net 9 "Net-(P2-Pad2)")
+  (net 10 "Net-(P2-Pad3)")
+  (net 11 GND)
+  (net 12 "Net-(P2-Pad5)")
+  (net 13 "Net-(P2-Pad6)")
+  (net 14 "Net-(P2-Pad7)")
+
+  (net_class Default "This is the default net class."
+    (clearance 0.2)
+    (trace_width 0.25)
+    (via_dia 0.6)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net GND)
+    (add_net "Net-(P1-Pad1)")
+    (add_net "Net-(P1-Pad2)")
+    (add_net "Net-(P1-Pad3)")
+    (add_net "Net-(P1-Pad5)")
+    (add_net "Net-(P1-Pad6)")
+    (add_net "Net-(P1-Pad7)")
+    (add_net "Net-(P2-Pad1)")
+    (add_net "Net-(P2-Pad2)")
+    (add_net "Net-(P2-Pad3)")
+    (add_net "Net-(P2-Pad5)")
+    (add_net "Net-(P2-Pad6)")
+    (add_net "Net-(P2-Pad7)")
+    (add_net VCC)
+  )
+
+  (module Pin_Headers:Pin_Header_Straight_1x07 (layer B.Cu) (tedit 5AB3B738) (tstamp 5AB3B634)
+    (at 157.48 114.3)
+    (descr "Through hole pin header")
+    (tags "pin header")
+    (path /5AB3ACB3)
+    (fp_text reference P2 (at 0 5.1) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value CONN_01X07 (at 0 3.1) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -1.75 1.75) (end -1.75 -17) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 1.75 1.75) (end 1.75 -17) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.75 1.75) (end 1.75 1.75) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.75 -17) (end 1.75 -17) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 1.27 -1.27) (end 1.27 -16.51) (layer B.SilkS) (width 0.15))
+    (fp_line (start 1.27 -16.51) (end -1.27 -16.51) (layer B.SilkS) (width 0.15))
+    (fp_line (start -1.27 -16.51) (end -1.27 -1.27) (layer B.SilkS) (width 0.15))
+    (fp_line (start 1.55 1.55) (end 1.55 0) (layer B.SilkS) (width 0.15))
+    (fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer B.SilkS) (width 0.15))
+    (fp_line (start -1.55 0) (end -1.55 1.55) (layer B.SilkS) (width 0.15))
+    (fp_line (start -1.55 1.55) (end 1.55 1.55) (layer B.SilkS) (width 0.15))
+    (pad 1 thru_hole circle (at 0 0) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
+      (net 8 "Net-(P2-Pad1)"))
+    (pad 2 thru_hole circle (at 0 -2.54) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
+      (net 9 "Net-(P2-Pad2)"))
+    (pad 3 thru_hole circle (at 0 -5.08) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
+      (net 10 "Net-(P2-Pad3)"))
+    (pad 4 thru_hole rect (at 0 -7.62) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
+      (net 11 GND))
+    (pad 5 thru_hole circle (at 0 -10.16) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
+      (net 12 "Net-(P2-Pad5)"))
+    (pad 6 thru_hole circle (at 0 -12.7) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
+      (net 13 "Net-(P2-Pad6)"))
+    (pad 7 thru_hole circle (at 0 -15.24) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
+      (net 14 "Net-(P2-Pad7)"))
+    (model Pin_Headers.3dshapes/Pin_Header_Straight_1x07.wrl
+      (at (xyz 0 -0.3 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 90))
+    )
+  )
+
+  (module Pin_Headers:Pin_Header_Straight_1x07 (layer B.Cu) (tedit 5AB3B6DD) (tstamp 5AB3B629)
+    (at 139.7 99.06 180)
+    (descr "Through hole pin header")
+    (tags "pin header")
+    (path /5AB3AD07)
+    (fp_text reference P1 (at 0 5.1 180) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value CONN_01X07 (at 0 3.1 180) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_line (start -1.75 1.75) (end -1.75 -17) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 1.75 1.75) (end 1.75 -17) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.75 1.75) (end 1.75 1.75) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.75 -17) (end 1.75 -17) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 1.27 -1.27) (end 1.27 -16.51) (layer B.SilkS) (width 0.15))
+    (fp_line (start 1.27 -16.51) (end -1.27 -16.51) (layer B.SilkS) (width 0.15))
+    (fp_line (start -1.27 -16.51) (end -1.27 -1.27) (layer B.SilkS) (width 0.15))
+    (fp_line (start 1.55 1.55) (end 1.55 0) (layer B.SilkS) (width 0.15))
+    (fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer B.SilkS) (width 0.15))
+    (fp_line (start -1.55 0) (end -1.55 1.55) (layer B.SilkS) (width 0.15))
+    (fp_line (start -1.55 1.55) (end 1.55 1.55) (layer B.SilkS) (width 0.15))
+    (pad 1 thru_hole circle (at 0 0 180) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
+      (net 1 "Net-(P1-Pad1)"))
+    (pad 2 thru_hole circle (at 0 -2.54 180) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
+      (net 2 "Net-(P1-Pad2)"))
+    (pad 3 thru_hole circle (at 0 -5.08 180) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
+      (net 3 "Net-(P1-Pad3)"))
+    (pad 4 thru_hole oval (at 0 -7.62 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
+      (net 4 VCC))
+    (pad 5 thru_hole circle (at 0 -10.16 180) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
+      (net 5 "Net-(P1-Pad5)"))
+    (pad 6 thru_hole circle (at 0 -12.7 180) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
+      (net 6 "Net-(P1-Pad6)"))
+    (pad 7 thru_hole circle (at 0 -15.24 180) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
+      (net 7 "Net-(P1-Pad7)"))
+    (model Pin_Headers.3dshapes/Pin_Header_Straight_1x07.wrl
+      (at (xyz 0 -0.3 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 90))
+    )
+  )
+
+  (module Housings_SOIC:SOIC-14_3.9x8.7mm_Pitch1.27mm (layer F.Cu) (tedit 54130A77) (tstamp 5AB3B646)
+    (at 148.59 106.68)
+    (descr "14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
+    (tags "SOIC 1.27")
+    (path /5AB3AE31)
+    (attr smd)
+    (fp_text reference U1 (at 0 -5.375) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value LMV824M (at 0 5.375) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start -3.7 -4.65) (end -3.7 4.65) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 3.7 -4.65) (end 3.7 4.65) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -3.7 -4.65) (end 3.7 -4.65) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -3.7 4.65) (end 3.7 4.65) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.075 -4.45) (end -2.075 -4.335) (layer F.SilkS) (width 0.15))
+    (fp_line (start 2.075 -4.45) (end 2.075 -4.335) (layer F.SilkS) (width 0.15))
+    (fp_line (start 2.075 4.45) (end 2.075 4.335) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.075 4.45) (end -2.075 4.335) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.075 -4.45) (end 2.075 -4.45) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.075 4.45) (end 2.075 4.45) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.075 -4.335) (end -3.45 -4.335) (layer F.SilkS) (width 0.15))
+    (pad 1 smd rect (at -2.7 -3.81) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 1 "Net-(P1-Pad1)"))
+    (pad 2 smd rect (at -2.7 -2.54) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 2 "Net-(P1-Pad2)"))
+    (pad 3 smd rect (at -2.7 -1.27) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 3 "Net-(P1-Pad3)"))
+    (pad 4 smd rect (at -2.7 0) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 4 VCC))
+    (pad 5 smd rect (at -2.7 1.27) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 5 "Net-(P1-Pad5)"))
+    (pad 6 smd rect (at -2.7 2.54) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 6 "Net-(P1-Pad6)"))
+    (pad 7 smd rect (at -2.7 3.81) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 7 "Net-(P1-Pad7)"))
+    (pad 8 smd rect (at 2.7 3.81) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 8 "Net-(P2-Pad1)"))
+    (pad 9 smd rect (at 2.7 2.54) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 9 "Net-(P2-Pad2)"))
+    (pad 10 smd rect (at 2.7 1.27) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 10 "Net-(P2-Pad3)"))
+    (pad 11 smd rect (at 2.7 0) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 11 GND))
+    (pad 12 smd rect (at 2.7 -1.27) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 12 "Net-(P2-Pad5)"))
+    (pad 13 smd rect (at 2.7 -2.54) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 13 "Net-(P2-Pad6)"))
+    (pad 14 smd rect (at 2.7 -3.81) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 14 "Net-(P2-Pad7)"))
+    (model Housings_SOIC.3dshapes/SOIC-14_3.9x8.7mm_Pitch1.27mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (gr_text ▼ (at 145.796 101.6) (layer F.Cu)
+    (effects (font (size 0.5 0.5) (thickness 0.05)))
+  )
+  (gr_text CO (at 159.004 114.3) (layer F.Cu) (tstamp 5AB3C0D4)
+    (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
+  )
+  (gr_text CI- (at 159.004 111.76) (layer F.Cu) (tstamp 5AB3C0C7)
+    (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
+  )
+  (gr_text CI+ (at 159.004 109.22) (layer F.Cu) (tstamp 5AB3C0B2)
+    (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
+  )
+  (gr_text DO (at 159.004 99.06) (layer F.Cu) (tstamp 5AB3C09B)
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diff --git a/boards/OPV/OPV.pro b/boards/OPV/OPV.pro
new file mode 100644
index 0000000..9a83d8c
--- /dev/null
+++ b/boards/OPV/OPV.pro
@@ -0,0 +1,60 @@
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diff --git a/boards/OPV/OPV.sch b/boards/OPV/OPV.sch
new file mode 100644
index 0000000..f5ba021
--- /dev/null
+++ b/boards/OPV/OPV.sch
@@ -0,0 +1,289 @@
+EESchema Schematic File Version 2
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+LIBS:device
+LIBS:transistors
+LIBS:conn
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+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
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diff --git a/boards/Spannungsversorgung-cache.lib b/boards/Spannungsversorgung/Spannungsversorgung-cache.lib
similarity index 100%
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rename to boards/Spannungsversorgung/Spannungsversorgung-cache.lib
diff --git a/boards/Spannungsversorgung.kicad_pcb b/boards/Spannungsversorgung/Spannungsversorgung.kicad_pcb
similarity index 100%
rename from boards/Spannungsversorgung.kicad_pcb
rename to boards/Spannungsversorgung/Spannungsversorgung.kicad_pcb
diff --git a/boards/Spannungsversorgung.pro b/boards/Spannungsversorgung/Spannungsversorgung.pro
similarity index 100%
rename from boards/Spannungsversorgung.pro
rename to boards/Spannungsversorgung/Spannungsversorgung.pro
diff --git a/boards/Spannungsversorgung.rules b/boards/Spannungsversorgung/Spannungsversorgung.rules
similarity index 100%
rename from boards/Spannungsversorgung.rules
rename to boards/Spannungsversorgung/Spannungsversorgung.rules
diff --git a/boards/Spannungsversorgung.sch b/boards/Spannungsversorgung/Spannungsversorgung.sch
similarity index 100%
rename from boards/Spannungsversorgung.sch
rename to boards/Spannungsversorgung/Spannungsversorgung.sch
diff --git a/boards/components/ceae2594m-5.dcm b/boards/Spannungsversorgung/components/ceae2594m-5.dcm
similarity index 100%
rename from boards/components/ceae2594m-5.dcm
rename to boards/Spannungsversorgung/components/ceae2594m-5.dcm
diff --git a/boards/components/ceae2594m-5.lib b/boards/Spannungsversorgung/components/ceae2594m-5.lib
similarity index 100%
rename from boards/components/ceae2594m-5.lib
rename to boards/Spannungsversorgung/components/ceae2594m-5.lib
diff --git a/boards/footprints/Inductor18.4x15.kicad_mod b/boards/Spannungsversorgung/footprints/Inductor18.4x15.kicad_mod
similarity index 100%
rename from boards/footprints/Inductor18.4x15.kicad_mod
rename to boards/Spannungsversorgung/footprints/Inductor18.4x15.kicad_mod
diff --git a/boards/footprints/USB A.kicad_mod b/boards/Spannungsversorgung/footprints/USB A.kicad_mod
similarity index 100%
rename from boards/footprints/USB A.kicad_mod
rename to boards/Spannungsversorgung/footprints/USB A.kicad_mod
diff --git a/boards/footprints/USB-A-SMT-8231.kicad_mod b/boards/Spannungsversorgung/footprints/USB-A-SMT-8231.kicad_mod
similarity index 100%
rename from boards/footprints/USB-A-SMT-8231.kicad_mod
rename to boards/Spannungsversorgung/footprints/USB-A-SMT-8231.kicad_mod
diff --git a/boards/fp-lib-table b/boards/Spannungsversorgung/fp-lib-table
similarity index 100%
rename from boards/fp-lib-table
rename to boards/Spannungsversorgung/fp-lib-table
diff --git a/documents/OPV-F.Cu.pdf b/documents/OPV-F.Cu.pdf
new file mode 100644
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