From 7a52315811646dff9239c7da4467bf7666efd809 Mon Sep 17 00:00:00 2001 From: Max Braungardt Date: Wed, 14 Mar 2018 11:40:56 +0100 Subject: [PATCH] Changed Power Input Connector to Barrel Jack --- boards/Spannungsversorgung-cache.lib | 45 +++-- boards/Spannungsversorgung.kicad_pcb | 247 ++++++++++++++------------- boards/Spannungsversorgung.pro | 12 +- boards/Spannungsversorgung.rules | 77 +++++++++ boards/Spannungsversorgung.sch | 242 +++++++++++++------------- 5 files changed, 358 insertions(+), 265 deletions(-) create mode 100644 boards/Spannungsversorgung.rules diff --git a/boards/Spannungsversorgung-cache.lib b/boards/Spannungsversorgung-cache.lib index bc09c43..6bd6082 100644 --- a/boards/Spannungsversorgung-cache.lib +++ b/boards/Spannungsversorgung-cache.lib @@ -1,6 +1,27 @@ EESchema-LIBRARY Version 2.3 #encoding utf-8 # +# BARREL_JACK +# +DEF BARREL_JACK CON 0 40 Y Y 1 F N +F0 "CON" 0 250 50 H V C CNN +F1 "BARREL_JACK" 0 -200 50 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +A -300 99 49 -900 1788 0 1 0 N -300 50 -350 100 +A -300 101 49 900 -1788 0 1 0 N -300 150 -350 100 +S 100 150 0 50 0 1 0 N +P 2 0 1 0 -300 50 0 50 N +P 2 0 1 0 0 150 -300 150 N +P 3 0 1 0 100 0 -50 0 -50 -100 N +P 5 0 1 0 100 -100 -150 -100 -200 -50 -250 -100 -350 -100 N +X ~ 1 300 100 200 L 50 50 1 1 P +X ~ 2 300 -100 200 L 50 50 1 1 P +X ~ 3 300 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# # CEAE2594M-5.0 # DEF CEAE2594M-5.0 U 0 40 Y Y 1 F N @@ -202,30 +223,6 @@ X ~ 2 0 -150 50 U 50 50 1 1 P ENDDRAW ENDDEF # -# USB_A -# -DEF USB_A P 0 40 Y Y 1 F N -F0 "P" 200 -200 50 H V C CNN -F1 "USB_A" -50 200 50 H V C CNN -F2 "" -50 -100 50 V V C CNN -F3 "" -50 -100 50 V V C CNN -$FPLIST - USB* -$ENDFPLIST -DRAW -S -250 -150 150 150 0 1 0 N -S -205 -150 -195 -120 0 1 0 N -S -105 -150 -95 -120 0 1 0 N -S -5 -150 5 -120 0 1 0 N -S 95 -150 105 -120 0 1 0 N -X VCC 1 -200 -300 150 U 50 50 1 1 W -X D- 2 -100 -300 150 U 50 50 1 1 P -X D+ 3 0 -300 150 U 50 50 1 1 P -X GND 4 100 -300 150 U 50 50 1 1 W -X shield 5 300 100 150 L 50 50 1 1 P -ENDDRAW -ENDDEF -# # VCC # DEF VCC #PWR 0 0 Y Y 1 F P diff --git a/boards/Spannungsversorgung.kicad_pcb b/boards/Spannungsversorgung.kicad_pcb index 890c096..d174240 100644 --- a/boards/Spannungsversorgung.kicad_pcb +++ b/boards/Spannungsversorgung.kicad_pcb @@ -1,12 +1,12 @@ (kicad_pcb (version 4) (host pcbnew 4.0.2+dfsg1-stable) (general - (links 30) - (no_connects 2) - (area 80.43 58.391666 121.879 114.64) + (links 26) + (no_connects 0) + (area 81.124379 58.391666 121.960504 114.64) (thickness 1.6) (drawings 0) - (tracks 92) + (tracks 108) (zones 0) (modules 14) (nets 10) @@ -58,8 +58,8 @@ (mod_edge_width 0.15) (mod_text_size 1 1) (mod_text_width 0.15) - (pad_size 1.7272 1.7272) - (pad_drill 1.016) + (pad_size 6.096 6.096) + (pad_drill 0) (pad_to_mask_clearance 0.2) (aux_axis_origin 0 0) (visible_elements FFFFFF7F) @@ -277,31 +277,6 @@ (net 5 "Net-(D2-Pad1)")) ) - (module "footprints:USB A" (layer F.Cu) (tedit 5AA1E3CA) (tstamp 5AA1E17B) - (at 80.88 81.5 270) - (path /5AA1A654) - (fp_text reference P1 (at 2.2225 -0.762 270) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value USB_A (at 6.6675 -10.16 270) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 0 -16.5) (end 12.6 -16.5) (layer F.SilkS) (width 0.15)) - (fp_line (start 12.6 -16.5) (end 12.6 0) (layer F.SilkS) (width 0.15)) - (fp_line (start 0 0) (end 12.6 0) (layer F.SilkS) (width 0.15)) - (fp_line (start 0 0) (end 0 -16.5) (layer F.SilkS) (width 0.15)) - (pad Dong thru_hole oval (at 13.2 -10 270) (size 2.5 3.5) (drill oval 1 2.1) (layers *.Cu *.Mask F.SilkS)) - (pad D+ thru_hole rect (at 7.4 -13.1 270) (size 1.5 1.5) (drill 0.8) (layers *.Cu *.Mask F.SilkS) - (net 2 GND)) - (pad GND thru_hole circle (at 5 -13.1 270) (size 1.5 1.5) (drill 0.8) (layers *.Cu *.Mask F.SilkS) - (net 6 VCC)) - (pad D- thru_hole rect (at 7.4 -15.5 270) (size 1.5 1.5) (drill 0.8) (layers *.Cu *.Mask F.SilkS) - (net 2 GND)) - (pad VCC thru_hole circle (at 5 -15.5 270) (size 1.5 1.5) (drill 0.8) (layers *.Cu *.Mask F.SilkS) - (net 6 VCC)) - (pad Ding thru_hole oval (at -0.6 -10 270) (size 2.5 3.5) (drill oval 1 2.1) (layers *.Cu *.Mask F.SilkS)) - ) - (module Pin_Headers:Pin_Header_Straight_2x02 (layer B.Cu) (tedit 5AA1E337) (tstamp 5AA1E18F) (at 99.06 86.36 270) (descr "Through hole pin header") @@ -472,7 +447,7 @@ ) ) - (module TO_SOT_Packages_SMD:TO-252-2Lead (layer F.Cu) (tedit 5AA1EA99) (tstamp 5AA1E1E5) + (module TO_SOT_Packages_SMD:TO-252-2Lead (layer F.Cu) (tedit 5AA8F845) (tstamp 5AA1E1E5) (at 110.49 73.66 270) (descr "DPAK / TO-252 2-lead smd package") (tags "dpak TO-252") @@ -495,12 +470,10 @@ (fp_line (start -3.429 -1.524) (end -3.429 -9.398) (layer F.SilkS) (width 0.15)) (fp_line (start -3.429 -9.525) (end 3.429 -9.525) (layer F.SilkS) (width 0.15)) (fp_line (start 3.429 -9.398) (end 3.429 -7.62) (layer F.SilkS) (width 0.15)) - (pad G smd rect (at -2.286 0 270) (size 1.651 3.048) (layers F.Cu F.Paste F.Mask) - (net 4 "Net-(D1-Pad2)")) + (pad G smd rect (at -2.286 0 270) (size 1.651 3.048) (layers F.Cu F.Paste F.Mask)) (pad D smd rect (at 0 -6.35 270) (size 6.096 6.096) (layers F.Cu F.Paste F.Mask) (net 6 VCC)) - (pad S smd rect (at 2.286 0 270) (size 1.651 3.048) (layers F.Cu F.Paste F.Mask) - (net 1 "Net-(C1-Pad1)")) + (pad S smd rect (at 2.286 0 270) (size 1.651 3.048) (layers F.Cu F.Paste F.Mask)) (model TO_SOT_Packages_SMD.3dshapes/TO-252-2Lead.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -572,97 +545,137 @@ (net 5 "Net-(D2-Pad1)")) ) - (segment (start 114.046 81.915) (end 116.095297 81.915) (width 0.25) (layer F.Cu) (net 1)) - (segment (start 116.095297 81.915) (end 116.095297 83.199103) (width 0.25) (layer F.Cu) (net 1)) - (segment (start 116.095297 83.199103) (end 110.3944 88.9) (width 0.25) (layer F.Cu) (net 1)) - (segment (start 114.046 81.915) (end 110.49 81.915) (width 0.25) (layer F.Cu) (net 1)) + (module Connect:BARREL_JACK (layer B.Cu) (tedit 0) (tstamp 5AA7E807) + (at 88.9 88.9) + (descr "DC Barrel Jack") + (tags "Power Jack") + (path /5AA7E818) + (fp_text reference CON1 (at 10.09904 0 270) (layer B.SilkS) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_text value BARREL_JACK (at 0 5.99948) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_line (start -4.0005 4.50088) (end -4.0005 -4.50088) (layer B.SilkS) (width 0.15)) + (fp_line (start -7.50062 4.50088) (end -7.50062 -4.50088) (layer B.SilkS) (width 0.15)) + (fp_line (start -7.50062 -4.50088) (end 7.00024 -4.50088) (layer B.SilkS) (width 0.15)) + (fp_line (start 7.00024 -4.50088) (end 7.00024 4.50088) (layer B.SilkS) (width 0.15)) + (fp_line (start 7.00024 4.50088) (end -7.50062 4.50088) (layer B.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 6.20014 0) (size 3.50012 3.50012) (drill oval 1.00076 2.99974) (layers *.Cu *.Mask B.SilkS) + (net 6 VCC)) + (pad 2 thru_hole rect (at 0.20066 0) (size 3.50012 3.50012) (drill oval 1.00076 2.99974) (layers *.Cu *.Mask B.SilkS) + (net 2 GND)) + (pad 3 thru_hole rect (at 3.2004 -4.699) (size 3.50012 3.50012) (drill oval 2.99974 1.00076) (layers *.Cu *.Mask B.SilkS) + (net 2 GND)) + ) + + (segment (start 116.095 83.1991) (end 110.394 88.9) (width 0.25) (layer F.Cu) (net 1)) + (segment (start 116.095 81.915) (end 116.095 83.1991) (width 0.25) (layer F.Cu) (net 1)) + (segment (start 114.046 81.915) (end 116.095 81.915) (width 0.25) (layer F.Cu) (net 1)) (segment (start 110.49 81.915) (end 110.49 75.946) (width 0.25) (layer F.Cu) (net 1)) - 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(segment (start 93.98 86.5) (end 94.58 86.5) (width 0.25) (layer F.Cu) (net 6)) - (segment (start 94.58 86.5) (end 96.38 86.5) (width 0.25) (layer F.Cu) (net 6)) ) diff --git a/boards/Spannungsversorgung.pro b/boards/Spannungsversorgung.pro index c7d8d1a..9cd90af 100644 --- a/boards/Spannungsversorgung.pro +++ b/boards/Spannungsversorgung.pro @@ -1,4 +1,4 @@ -update=Do 08 Mär 2018 22:03:33 CET +update=Mi 14 Mär 2018 11:37:13 CET version=1 last_client=kicad [pcbnew] @@ -59,3 +59,13 @@ LibName27=atmel LibName28=contrib LibName29=valves LibName30=components/ceae2594m-5 +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/boards/Spannungsversorgung.rules b/boards/Spannungsversorgung.rules new file mode 100644 index 0000000..75f8e0f --- /dev/null +++ b/boards/Spannungsversorgung.rules @@ -0,0 +1,77 @@ + +(rules PCB Spannungsversorgung + (snap_angle + fortyfive_degree + ) + (autoroute_settings + (fanout off) + (autoroute on) + (postroute on) + (vias off) + (via_costs 50) + (plane_via_costs 5) + (start_ripup_costs 100) + (start_pass_no 118) + (layer_rule F.Cu + (active on) + (preferred_direction vertical) + (preferred_direction_trace_costs 1.0) + (against_preferred_direction_trace_costs 2.4) + ) + (layer_rule B.Cu + (active off) + (preferred_direction horizontal) + (preferred_direction_trace_costs 1.0) + (against_preferred_direction_trace_costs 1.7) + ) + ) + (rule + (width 250.0) + (clear 200.2) + (clear 125.0 (type smd_to_turn_gap)) + (clear 50.0 (type smd_smd)) + ) + (padstack "Via[0-1]_600:400_um" + (shape + (circle F.Cu 600.0 0.0 0.0) + ) + (shape + (circle B.Cu 600.0 0.0 0.0) + ) + (attach off) + ) + (via + "Via[0-1]_600:400_um" "Via[0-1]_600:400_um" default + ) + (via + "Via[0-1]_600:400_um-kicad_default" "Via[0-1]_600:400_um" "kicad_default" + ) + (via_rule + default "Via[0-1]_600:400_um" + ) + (via_rule + "kicad_default" "Via[0-1]_600:400_um-kicad_default" + ) + (class default + (clearance_class default) + (via_rule default) + (rule + (width 250.0) + ) + (circuit + (use_layer F.Cu B.Cu) + ) + ) + (class "kicad_default" + "Net-(C1-Pad1)" GND "Net-(C2-Pad1)" "Net-(D1-Pad2)" "Net-(D2-Pad1)" VCC "Net-(U1-Pad1)" "Net-(U1-Pad2)" + "Net-(U1-Pad3)" + (clearance_class "kicad_default") + (via_rule kicad_default) + (rule + (width 250.0) + ) + (circuit + (use_layer F.Cu B.Cu) + ) + ) +) \ No newline at end of file diff --git a/boards/Spannungsversorgung.sch b/boards/Spannungsversorgung.sch index e7b0ae2..1447b17 100644 --- a/boards/Spannungsversorgung.sch +++ b/boards/Spannungsversorgung.sch @@ -56,17 +56,6 @@ F 3 "" H 4250 3100 60 0000 C CNN 0 1 1 0 $EndComp $Comp -L USB_A P1 -U 1 1 5AA1A654 -P 1200 3050 -F 0 "P1" H 1400 2850 50 0000 C CNN -F 1 "USB_A" H 1150 3250 50 0000 C CNN -F 2 "footprints:USB A" V 1150 2950 50 0001 C CNN -F 3 "" V 1150 2950 50 0000 C CNN - 1 1200 3050 - 0 -1 -1 0 -$EndComp -$Comp L IRF7309IPBF Q1 U 2 1 5AA1A8CA P 2600 2700 @@ -165,63 +154,7 @@ F 3 "" H 6250 1850 50 0000 C CNN 1 6250 3050 0 1 1 0 $EndComp -Wire Wire Line - 1650 3250 1500 3250 -Wire Wire Line - 1650 2500 1650 3250 -Wire Wire Line - 1650 2950 1500 2950 -Connection ~ 1650 2950 NoConn ~ 2400 2600 -Wire Wire Line - 1500 3150 1550 3150 -Wire Wire Line - 1550 3050 1550 3700 -Wire Wire Line - 1550 3050 1500 3050 -Connection ~ 1550 3150 -Connection ~ 2100 3700 -Connection ~ 2200 3700 -Wire Wire Line - 2650 2900 2650 3000 -Wire Wire Line - 2650 3000 3150 3000 -Connection ~ 2850 3000 -Connection ~ 3150 2600 -Wire Wire Line - 4150 3700 4150 3550 -Wire Wire Line - 4250 3700 4250 3550 -Connection ~ 4150 3700 -Wire Wire Line - 4450 3600 4450 3550 -Wire Wire Line - 4950 3600 4450 3600 -Connection ~ 4250 3700 -Wire Wire Line - 4150 2500 4150 2650 -Wire Wire Line - 2100 2850 2100 2500 -Connection ~ 2100 2500 -Wire Wire Line - 2200 2850 2200 2500 -Connection ~ 2200 2500 -Wire Wire Line - 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